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VLSI Specification, Verification and Synthesis

  • Graham Birtwistle
  • P. A. Subrahmanyam

Table of contents

  1. Front Matter
    Pages i-xi
  2. Michael J. C. Gordon
    Pages 73-128
  3. David R. Musser, Paliath Narendran, William J. Premerlani
    Pages 217-233
  4. Paliath Narendran, Jonathan Stillman
    Pages 235-255
  5. Bruce S. Davie, George J. Milne
    Pages 257-265
  6. Thomas F. Melham
    Pages 267-291
  7. Glynn Winskel
    Pages 323-347
  8. Steven D. Johnson, Bhaskar Bose, C. David Boyer
    Pages 349-383

About this book

Introduction

VLSI Specification, Verification and Synthesis Proceedings of a workshop held in Calgary from 12-16 January 1987. The collection of papers in this book represents some of the discussions and presentations at a workshop on hardware verification held in Calgary, January 12-16 1987. The thrust of the workshop was to give the floor to a few leading researchers involved in the use of formal approaches to VLSI design, and provide them ample time to develop not only their latest ideas but also the evolution of these ideas. In contrast to simulation, where the objective is to assist in detecting errors in system behavior in the case of some selected inputs, the intent of hardware verification is to formally prove that a chip design meets a specification of its intended behavior (for all acceptable inputs). There are several important applications where formal verification of designs may be argued to be cost-effective. Examples include hardware components used in "safety critical" applications such as flight control, industrial plants, and medical life-support systems (such as pacemakers). The problems are of such magnitude in certain defense applications that the UK Ministry of Defense feels it cannot rely on commercial chips and has embarked on a program of producing formally verified chips to its own specification. Hospital, civil aviation, and transport boards in the UK will also use these chips. A second application domain for verification is afforded by industry where specific chips may be used in high volume or be remotely placed.

Keywords

Hardware VLSI design formal verification simulation verification

Editors and affiliations

  • Graham Birtwistle
    • 1
  • P. A. Subrahmanyam
    • 2
  1. 1.University of CalgaryCanada
  2. 2.AT&T Bell LaboratoriesUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4613-2007-4
  • Copyright Information Springer-Verlag US 1988
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-9197-8
  • Online ISBN 978-1-4613-2007-4
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site