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A Systolic Array Optimizing Compiler

  • Monica S. Lam

Table of contents

  1. Front Matter
    Pages i-xxii
  2. Monica S. Lam
    Pages 1-10
  3. Monica S. Lam
    Pages 11-23
  4. Monica S. Lam
    Pages 25-68
  5. Monica S. Lam
    Pages 69-82
  6. Monica S. Lam
    Pages 83-124
  7. Monica S. Lam
    Pages 125-145
  8. Monica S. Lam
    Pages 147-185
  9. Monica S. Lam
    Pages 187-191
  10. Back Matter
    Pages 193-201

About this book

Introduction

This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu­ tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.

Keywords

Scheduling Skew communication optimization parallel computing processor

Authors and affiliations

  • Monica S. Lam
    • 1
  1. 1.Carnegie Mellon UniversityUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4613-1705-0
  • Copyright Information Springer-Verlag US 1989
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-8961-6
  • Online ISBN 978-1-4613-1705-0
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site