From Contamination to Defects, Faults and Yield Loss

Simulation and Applications

  • Jitendra B. Khare
  • Wojciech Maly

Part of the Frontiers in Electronic Testing book series (FRET, volume 5)

Table of contents

  1. Front Matter
    Pages i-xv
  2. Jitendra B. Khare, Wojciech Maly
    Pages 1-12
  3. Jitendra B. Khare, Wojciech Maly
    Pages 13-35
  4. Jitendra B. Khare, Wojciech Maly
    Pages 37-46
  5. Jitendra B. Khare, Wojciech Maly
    Pages 47-83
  6. Jitendra B. Khare, Wojciech Maly
    Pages 85-114
  7. Jitendra B. Khare, Wojciech Maly
    Pages 115-119
  8. Jitendra B. Khare, Wojciech Maly
    Pages 121-122
  9. Back Matter
    Pages 123-150

About this book


Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.
Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing.
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems.
Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.


CMOS VLSI circuit design computer integrated circuit manufacturing material mechanism model modeling physics simulation testing transistor

Authors and affiliations

  • Jitendra B. Khare
    • 1
  • Wojciech Maly
    • 1
  1. 1.Carnegie Mellon UniversityUSA

Bibliographic information

  • DOI
  • Copyright Information Springer-Verlag US 1996
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-8595-3
  • Online ISBN 978-1-4613-1377-9
  • Series Print ISSN 0929-1296
  • Buy this book on publisher's site