Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

  • Sung Kyu Lim

Table of contents

  1. Front Matter
    Pages i-xxviii
  2. High Performance and Low Power 3D IC Designs

    1. Front Matter
      Pages 1-1
    2. Sung Kyu Lim
      Pages 41-73
    3. Sung Kyu Lim
      Pages 75-97
    4. Sung Kyu Lim
      Pages 99-128
    5. Sung Kyu Lim
      Pages 129-151
    6. Sung Kyu Lim
      Pages 153-185
  3. Electrical Reliability in 3D IC Designs

    1. Front Matter
      Pages 187-187
    2. Sung Kyu Lim
      Pages 205-229
  4. Thermal Reliability in 3D IC Designs

    1. Front Matter
      Pages 251-251
    2. Sung Kyu Lim
      Pages 309-341
  5. Mechanical Reliability in 3D IC Designs

  6. Other Topics

About this book


This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process.

  • Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability.
  • Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs.
  • Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance.
  • Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.


Design for Manufacturability Design for Reliability Design for Testability Electronic Design Automation Embedded Systems GDSII layouts Integrated Circuits and Systems TSV Three Dimensional Integrated Circuits Through Silicon Via

Authors and affiliations

  • Sung Kyu Lim
    • 1
  1. 1.School of Electrical &, Computer EngineeringGeorgia Institute of TechnologyATLANTAUSA

Bibliographic information

  • DOI
  • Copyright Information Springer Science+Business Media New York 2013
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4419-9541-4
  • Online ISBN 978-1-4419-9542-1
  • Buy this book on publisher's site