Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Table of contents (20 chapters)
-
Front Matter
Pages i-xxviii
-
High Performance and Low Power 3D IC Designs
-
Front Matter
Pages 1-1
-
Chapter
Pages 3-40
Regular Versus Irregular TSV Placement for 3D IC
-
Chapter
Pages 41-73
-
Chapter
Pages 75-97
-
Chapter
Pages 99-128
Low Power Clock Routing for 3D IC
-
Chapter
Pages 129-151
Power Delivery Network Design for 3D IC
-
Chapter
Pages 153-185
3D Clock Routing for Pre-bond Testability
-
-
Electrical Reliability in 3D IC Designs
-
Front Matter
Pages 187-187
-
Chapter
Pages 189-203
TSV-to-TSV Coupling Analysis and Optimization
-
Chapter
Pages 205-229
TSV Current Crowding and Power Integrity
-
Chapter
Pages 231-250
Modeling of Atomic Concentration at the Wire-to-TSV Interface
-
-
Thermal Reliability in 3D IC Designs
-
Front Matter
Pages 251-251
-
Chapter
Pages 253-283
Multi-objective Architectural Floorplanning for 3D IC
-
Chapter
Pages 285-308
Thermal-Aware Gate-Level Placement for 3D IC
-
Chapter
Pages 309-341
3D IC Cooling with Micro-Fluidic Channels
-
-
Mechanical Reliability in 3D IC Designs
-
Front Matter
Pages 343-343
-
Chapter
Pages 345-378
Mechanical Reliability Analysis and Optimization for 3D ICs
-
Chapter
Pages 379-414
Impact of Mechanical Stress on Timing Variation for 3D IC
-
Chapter
Pages 415-441
Chip/Package Co-analysis of Mechanical Stress for 3D IC
-
Chapter
Pages 443-465
3D Chip/Package Co-analysis of Stress-Induced Timing Variations
-
Chapter
Pages 467-489
TSV Interfacial Crack Analysis and Optimization
-
-
Other Topics
-
Front Matter
Pages 491-491
-
Chapter
Pages 493-514
Ultra High Density Logic Designs Using Monolithic 3D Integration
-
Chapter
Pages 515-535
Impact of TSV Scaling on 3D IC Design Quality
-
Chapter
Pages 537-560
3D-MAPS: 3D Massively Parallel Processor with Stacked Memory
-
Continue reading...
To view the rest of this content please follow the download PDF link above.
