High-Level Verification

Methods and Tools for Verification of System-Level Designs

  • Sudipta Kundu
  • Sorin Lerner
  • Rajesh K. Gupta

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 1-9
  3. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 11-23
  4. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 25-35
  5. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 37-50
  6. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 51-66
  7. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 97-121
  8. Zachary Tatlock
    Pages 123-145
  9. Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
    Pages 147-150
  10. Back Matter
    Pages 151-167

About this book

Introduction

This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers.

The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically.

The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.
  • Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification;
  • Uses a combination of formal techniques to do scalable verification of system designs completely automatically;
  • Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL;
  • Written by researchers working in mainstream hardware and software design and includes results from both academia and industry









Keywords

Design Automation Design Validation Design Verification EDA Embedded Systems Equivalence Checking Heterogeneous System-on-Chip High-level Synthesis Microelectronic Systems Model Checking System Level Design System Level Verification

Authors and affiliations

  • Sudipta Kundu
    • 1
  • Sorin Lerner
    • 2
  • Rajesh K. Gupta
    • 3
  1. 1.Synopsis, Inc.HillsboroUSA
  2. 2., Dept of Computer Science and EngineeringUniversity of California, San DiegoLa JollaUSA
  3. 3., Dept of Computer Science and EngineeringUniversity of California, San DiegoLa JollaUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4419-9359-5
  • Copyright Information Springer Science+Business Media, LLC 2011
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4419-9358-8
  • Online ISBN 978-1-4419-9359-5
  • About this book