Table of contents
About this book
Power Distribution Networks with On-Chip Decoupling Capacitors, 2nd edition is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. This book provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors. The book provides insight and intuition into the behavior and design of on-chip power distribution systems.
This book has four primary objectives. The first objective is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the terminals of the on-chip circuitry. The second objective is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for efficiently placing on-chip decoupling capacitors in nanoscale integrated circuits. Finally, the fourth objective is to suggest novel architectures for distributing power across an integrated circuit, as well as provide new methodologies to efficiently analyze and design on-chip power grids.
Organized into subareas to provide a more intuitive flow to the reader, this edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.