Digital System Test and Testable Design

Using HDL Models and Architectures

  • Zainalabedin Navabi

Table of contents

  1. Front Matter
    Pages i-xvii
  2. Zainalabedin Navabi
    Pages 1-20
  3. Zainalabedin Navabi
    Pages 21-62
  4. Zainalabedin Navabi
    Pages 63-101
  5. Zainalabedin Navabi
    Pages 103-142
  6. Zainalabedin Navabi
    Pages 143-174
  7. Zainalabedin Navabi
    Pages 175-212
  8. Zainalabedin Navabi
    Pages 213-259
  9. Zainalabedin Navabi
    Pages 261-294
  10. Zainalabedin Navabi
    Pages 295-344
  11. Zainalabedin Navabi
    Pages 345-373
  12. Zainalabedin Navabi
    Pages 375-391
  13. Back Matter
    Pages 393-435

About this book

Introduction

Digital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware / software environment facilitates description of complex test programs and test strategies. •Combines design and test •Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate •Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns •Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods •Virtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under test •Verilog descriptions of scan designs and BIST architectures are available that can be used in actual designs •PLI test utilities developed in-text are available for download •Introductory Video for Verilog basics, software developed in-text, and PLI basics available for download •Powerpoint slides available for each chapter

Keywords

BIST BIST Architetures Design for Test Digital System Test Electronic Testing Fault Modeling Fault Simulation HDL Hardware Description Language Memory Testing PLI Testable Design Zainalabedin

Authors and affiliations

  • Zainalabedin Navabi
    • 1
  1. 1.Dept. Electrical & Computer, EngineeringWorcester Polytechnic InstituteWorcesterUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4419-7548-5
  • Copyright Information Springer Science+Business Media, LLC 2011
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-1-4419-7547-8
  • Online ISBN 978-1-4419-7548-5
  • About this book