Low-Power Variation-Tolerant Design in Nanometer Silicon

  • Swarup Bhunia
  • Saibal Mukhopadhyay

Table of contents

  1. Front Matter
    Pages i-xv
  2. Physics of Power Dissipations and Parameter Variations

    1. Front Matter
      Pages 1-1
    2. Aditya Bansal, Rahul M. Rao
      Pages 3-39
    3. Wei Zhang, James Williamson, Li Shang
      Pages 41-80
  3. Circuit-Level Design Solutions

    1. Front Matter
      Pages 81-81
    2. Sachin S. Sapatnekar
      Pages 109-149
    3. Hamid Mahmoodi
      Pages 151-183
    4. Bipul C. Paul, Arijit Raychowdhury
      Pages 185-207
  4. System-Level Design Solutions

    1. Front Matter
      Pages 209-209
    2. Meeta S. Gupta, Pradip Bose
      Pages 211-247
    3. Georgios Karakonstantis, Kaushik Roy
      Pages 249-292
    4. Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee
      Pages 293-333
  5. Low-Power and Robust Reconfigurable Computing

    1. Front Matter
      Pages 335-335
    2. Nikil Mehta, André DeHon
      Pages 337-363
    3. Nikil Mehta, André DeHon
      Pages 365-380
    4. Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon
      Pages 381-432
  6. Back Matter
    Pages 433-440

About this book

Introduction

Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. Coverage includes logic and memory design, modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. •Introduces readers to some of the most important challenges in low-power and variation-tolerant IC design in nanoscale technologies; •Presents a holistic view of Low-Power Variation-Tolerant Design, at different levels of design abstraction, starting from device to circuit, architecture and system; •Offers comprehensive coverage of modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems, micro-architecture, DSP, mixed-signal and FPGAs, including current industrial practices, technology scaling trends, and emerging challenges; •Describes in detail modeling and analysis of different variation effects (die-to-die and within-die, process and temporal) on low-power designs; Includes coverage of ultra low-power and robust sub-threshold design.

Keywords

DFM Design for Manufacturing EDA Electronic Design Automation Integrated Circuit Design Low Power IC Design Low Power Logic Design Low Power Memory Design Manufacturing Process Variation Nanometer IC Design Process Uncertainty Reliability Reliable IC Design Temperature-Aware Design

Editors and affiliations

  • Swarup Bhunia
    • 1
  • Saibal Mukhopadhyay
    • 2
  1. 1.Dept. Electrical Engineering &, Computer ScienceCase Western Reserve UniversityClevelandUSA
  2. 2.School of Electrical &, Computer EngineeringGeorgia Institute of TechnologyAtlantaUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4419-7418-1
  • Copyright Information Springer Science+Business Media, LLC 2011
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-1-4419-7417-4
  • Online ISBN 978-1-4419-7418-1
  • About this book