Low Power Networks-on-Chip

  • Cristina Silvano
  • Marcello Lajolo
  • Gianluca Palermo

Table of contents

  1. Front Matter
    Pages i-xix
  2. Low-Level Design Techniques

    1. Front Matter
      Pages 1-1
    2. Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar
      Pages 3-20
    3. Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano
      Pages 21-43
    4. Paul Ampadu, Bo Fu, David Wolpert, Qiaoyan Yu
      Pages 45-69
    5. Stanislavs Golubcovs, Alex Yakovlev
      Pages 71-109
  3. System-Level Design Techniques

    1. Front Matter
      Pages 111-111
    2. Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania
      Pages 113-150
    3. Yuho Jin, Ki Hwan Yum, Eun Jung Kim
      Pages 151-174
    4. Rudy Beraha, Isask’har Walter, Israel Cidon, Avinoam Kolodny
      Pages 175-195
  4. Future and Emerging Technologies

    1. Front Matter
      Pages 197-197
    2. Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
      Pages 199-222
    3. Jung Ho Ahn, Raymond G. Beausoleil, Nathan Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi et al.
      Pages 223-254
    4. Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman
      Pages 255-280
  5. Back Matter
    Pages 281-287

About this book


Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.


Embedded Systems High Speed Interconnect Low Power Design Network on Chip On-Chip Communication Architectures System-on-Chip

Editors and affiliations

  • Cristina Silvano
    • 1
  • Marcello Lajolo
    • 2
  • Gianluca Palermo
    • 3
  1. 1.Dipto. Elettronica e Informazione (DEI)Politecnico di MilanoMilanoItaly
  2. 2.NEC Laboratories America, Inc.PrincetonUSA
  3. 3.Dipto. Elettronica e Informazione (DEI)Politecnico di MilanoMilanoItaly

Bibliographic information