Book 2010

Power-Aware Testing and Test Strategies for Low Power Devices

Editors:

ISBN: 978-1-4419-0927-5 (Print) 978-1-4419-0928-2 (Online)

Table of contents (11 chapters)

  1. Front Matter

    Pages i-xxiii

    Download PDF (257KB)

  2. No Access

    Chapter

    Pages 1-29

    Fundamentals of VLSI Testing

    Laung-Terng Wang, Charles E. Stroud

  3. No Access

    Chapter

    Pages 31-63

    Power Issues During Test

    Sandip Kundu, Alodeep Sanyal

  4. No Access

    Chapter

    Pages 65-115

    Low-Power Test Pattern Generation

    Xiaoqing Wen, Seongmoon Wang

  5. No Access

    Chapter

    Pages 117-146

    Power-Aware Design-for-Test

    Hans-Joachim Wunderlich, Christian G. Zoellin

  6. No Access

    Chapter

    Pages 147-173

    Power-Aware Test Data Compression and BIST

    Sandeep Kumar Goel, Krishnendu Chakrabarty

  7. No Access

    Chapter

    Pages 175-211

    Power-Aware System-Level Test Planning

    Erik Larsson, C. P. Ravikumar

  8. No Access

    Chapter

    Pages 213-242

    Low-Power Design Techniques and Test Implications

    Kaushik Roy, Swarup Bhunia

  9. No Access

    Chapter

    Pages 243-271

    Test Strategies for Multivoltage Designs

    Saqib Khursheed, Bashir M. Al-Hashimi

  10. No Access

    Chapter

    Pages 273-293

    Test Strategies for Gated Clock Designs

    Brion Keller, Krishna Chakravadhanula

  11. No Access

    Chapter

    Pages 295-322

    Test of Power Management Structures

    Mark Kassab, Mohammad Tehranipoor

  12. No Access

    Chapter

    Pages 323-353

    EDA Solution for Power-Aware Design-for-Test

    Mokhtar Hirech

  13. Back Matter

    Pages 355-363

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