Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms

  • Andreas Wieferink
  • Heinrich Meyr
  • Rainer Leupers

Table of contents

  1. Front Matter
    Pages I-XIV
  2. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 1-6
  3. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 7-23
  4. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 25-40
  5. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 41-52
  6. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 53-65
  7. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 67-79
  8. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 81-90
  9. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 91-107
  10. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 109-126
  11. Andreas Wieferink, Heinrich Meyr, Rainer Leupers
    Pages 127-129
  12. Back Matter
    Pages 131-162

About this book

Introduction

The ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements.

However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration is only possible if accurate module simulators are generated automatically based on abstract specifications. As a matter of fact, CoWare’s BusCompiler allows generating accurate simulators for communication modules, and modeling languages such as LISA enable the same for processor cores.

In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms.

The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.

Keywords

Application-Specific Instruction-Set Processor (ASIP) Electronic System Level (ESL) Design Multi-Processor System-on-Chip (MP-SoC) Transaction Level Modeling (TLM) integrated circuit micro-alloy transistor organization

Authors and affiliations

  • Andreas Wieferink
    • 1
  • Heinrich Meyr
    • 2
  • Rainer Leupers
    • 2
  1. 1.CoWare, Inc52070 AachenGermany
  2. 2.ISS RWTH Aachen52056 AachenGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4020-8652-6
  • Copyright Information Springer Science+Business Media B.V. 2008
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-8574-1
  • Online ISBN 978-1-4020-8652-6