Digital VLSI Design with Verilog

A Textbook from Silicon Valley Technical Institute

  • John¬†Williams

Table of contents

  1. Front Matter
    Pages I-XXIII
  2. John Williams
    Pages 1-20
  3. John Williams
    Pages 21-42
  4. John Williams
    Pages 43-60
  5. John Williams
    Pages 61-82
  6. John Williams
    Pages 83-99
  7. John Williams
    Pages 101-112
  8. John Williams
    Pages 113-144
  9. John Williams
    Pages 145-168
  10. John Williams
    Pages 169-184
  11. John Williams
    Pages 185-194
  12. John Williams
    Pages 195-210
  13. John Williams
    Pages 211-230
  14. John Williams
    Pages 231-242
  15. John Williams
    Pages 243-258
  16. John Williams
    Pages 259-277
  17. John Williams
    Pages 279-293
  18. John Williams
    Pages 295-310
  19. John Williams
    Pages 311-335
  20. John Williams
    Pages 337-360

About this book

Introduction

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.
In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.
Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.
A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.
Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.

Keywords

HDL Scheduling VLSI simulation synthesis verification verilog

Authors and affiliations

  • John¬†Williams
    • 1
  1. 1.SVTI Inc. Silicon Valley Technical InstituteSan Jose CA 95110USA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4020-8446-1
  • Copyright Information John Michael Williams 2008
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-8445-4
  • Online ISBN 978-1-4020-8446-1
  • About this book