© 2008

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test


Part of the Frontiers In Electronic Testing book series (FRET, volume 40)

About this book


As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.

Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.


CMOS DOM RAM SRAM Transistor integrated circuit static-induction transistor

Authors and affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Dept. Electrical & Computer EngineeringUniversity of WaterlooN2L 3G1WaterlooCanada

About the authors

Prof. Sachdev has authored several successful books with Springer

Bibliographic information

  • Book Title CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
  • Book Subtitle Process-Aware SRAM Design and Test
  • Authors Andrei Pavlov
    Manoj Sachdev
  • Series Title Frontiers In Electronic Testing
  • DOI
  • Copyright Information Springer Netherlands 2008
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering Engineering (R0)
  • Hardcover ISBN 978-1-4020-8362-4
  • Softcover ISBN 978-90-481-7855-1
  • eBook ISBN 978-1-4020-8363-1
  • Series ISSN 0929-1296
  • Edition Number 1
  • Number of Pages XVI, 194
  • Number of Illustrations 0 b/w illustrations, 0 illustrations in colour
  • Topics Circuits and Systems
    Memory Structures
  • Buy this book on publisher's site