Design, Automation, and Test in Europe

Table of contents (36 chapters)

1. Front Matter

   Pages i-xii

   Download PDF (79KB)

2. System Level Design

   1. 

      Chapter

      Pages 3-14

      System Level Design: Past, Present, and Future

      Daniel D. Gajski

   2. 

      Chapter

      Pages 15-29

      Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

      Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop

   3. 

      Chapter

      Pages 31-45

      EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability

      Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil Dutt, Alex Nicolau

   4. 

      Chapter

      Pages 47-58

      RTOS Modeling for System Level Design

      Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski

   5. 

      Chapter

      Pages 59-72

      Context-Aware Performance Analysis for Efficient Embedded System Design

      Marek Jersak, Rafik Henia, Rolf Ernst

   6. 

      Chapter

      Pages 73-85

      Lock-Free Synchronization for Dynamic Embedded Real-Time Systems

      Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen

   7. 

      Chapter

      Pages 87-101

      What If You Could Design Tomorrow’s System Today?

      Neal Wingen

3. Networks on Chip

   1. 

      Chapter

      Pages 105-110

      Networks on Chips

      Giovanni De Micheli

   2. 

      Chapter

      Pages 111-123

      A Generic Architecture for On-Chip Packet-Switched Interconnections

      Pierre Guerrier, Alain Greiner

   3. 

      Chapter

      Pages 125-139

      Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

      E. Rijpkema, K. G. W. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen…

   4. 

      Chapter

      Pages 141-155

      Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures

      Jingcao Hu, Radu Marculescu

   5. 

      Chapter

      Pages 157-171

      xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip

      Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli

   6. 

      Chapter

      Pages 173-184

      A Network Traffic Generator Model for Fast Network-on-Chip Simulation

      Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Michael Storgaard, Jan Madsen…

4. Modeling, Simulation and Run-Time Management

   1. 

      Chapter

      Pages 187-193

      Modeling, Simulation and Run-Time Management

      Enrico Macii

   2. 

      Chapter

      Pages 195-206

      Dynamic Power Management for Nonstationary Service Requests

      Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli

   3. 

      Chapter

      Pages 207-219

      Quantitative Comparison of Power Management Algorithms

      Yung-Hsiang Lu, Eui-Young Chung, Tajana Šimunić, Luca Benini, Giovanni De Micheli

   4. 

      Chapter

      Pages 221-234

      Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives

      Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan, Wim Dehaene

   5. 

      Chapter

      Pages 235-251

      Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application

      Amith Singhee, Rob A. Rutenbar

   6. 

      Chapter

      Pages 253-265

      Compositional Specification of Behavioral Semantics

      Kai Chen, Janos Sztipanovits, Sandeep Neema

5. Design Technology for Advanced Digital Systems in CMOS and Beyond

   1. 

      Chapter

      Pages 269-273

      Design Technology for Advanced Digital Systems in CMOS and Beyond

      Hugo De Man, Hugo De Man