Table of contents
System Level Design
Networks on Chip
Modeling, Simulation and Run-Time Management
About this book
The Design, Automation and Test in Europe (DATE) conference celebrated in 2007 its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry.
The papers were grouped in six sections:
- System Level Design;
- Networks on Chip;
- Modeling, Simulation and Run-Time Management;
- Digital Systems in CMOS and Beyond;
- Physical Design and Validation; and
- Test and Verification.
The winners of the prestigious EDAA Lifetime Achievement Award as well as other recognized experts in their field wrote an introduction to each section, summarizing the history in their domain and indicating how the selected DATE papers contributed to it.