Design for Manufacturability and Yield for Nano-Scale CMOS

  • Charles C. Chiang
  • Jamil Kawa

Part of the Series on Integrated Circuits and Systems book series (ICIR)

Table of contents

  1. Front Matter
    Pages I-XXVII
  2. Charles C. Chiang, Jamil Kawa
    Pages 1-19
  3. Charles C. Chiang, Jamil Kawa
    Pages 21-51
  4. Charles C. Chiang, Jamil Kawa
    Pages 53-97
  5. Charles C. Chiang, Jamil Kawa
    Pages 99-150
  6. Charles C. Chiang, Jamil Kawa
    Pages 151-168
  7. Charles C. Chiang, Jamil Kawa
    Pages 169-193
  8. Charles C. Chiang, Jamil Kawa
    Pages 195-226
  9. Charles C. Chiang, Jamil Kawa
    Pages 227-242
  10. Back Matter
    Pages 243-254

About this book

Introduction

As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility.

Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.

Keywords

CAD (Computer aided design) CAE (Computer aided engineering) CMOS Standard classification computer-aided design (CAD) computer-aided engineering (CAE) design development integrated circuit layout model nano-scale simulation tables

Authors and affiliations

  • Charles C. Chiang
    • 1
  • Jamil Kawa
    • 2
  1. 1.Synopsys Inc.Mountain ViewUSA
  2. 2.Synopsys Inc.Mountain ViewUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4020-5188-3
  • Copyright Information Springer 2007
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-5187-6
  • Online ISBN 978-1-4020-5188-3
  • Series Print ISSN 1558-9412
  • About this book