Low-Power Deep Sub-Micron CMOS Logic

Sub-threshold Current Reduction

  • P. R. van der Meer
  • A. van Staveren
  • A. H. M. van Roermund

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 841)

Table of contents

  1. Front Matter
    Pages i-xiv
  2. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 1-4
  3. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 5-9
  4. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 11-52
  5. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 53-75
  6. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 77-91
  7. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 93-104
  8. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 105-120
  9. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 121-138
  10. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 139-140
  11. P. R. van der Meer, A. van Staveren, A. H. M. van Roermund
    Pages 141-144
  12. Back Matter
    Pages 145-154

About this book

Introduction

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in­ dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi­ pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa­ gation delay, which results in a lower data-processing speed performance.

Keywords

CMOS SECS 841 Transistor integrated circuit logic van der Meer zitter

Authors and affiliations

  • P. R. van der Meer
    • 1
  • A. van Staveren
    • 2
  • A. H. M. van Roermund
    • 3
  1. 1.Delft University of TechnologyDelftThe Netherlands
  2. 2.National Semiconductor CorporationDelftThe Netherlands
  3. 3.Eindhoven University of TechnologyEindhovenThe Netherlands

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4020-2849-6
  • Copyright Information Springer-Verlag US 2004
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4757-1057-1
  • Online ISBN 978-1-4020-2849-6
  • Series Print ISSN 0893-3405
  • About this book