Table of contents

  1. Front Matter
    Pages 1-19
  2. J. Bhasker, Rakesh Chadha
    Pages 1-14
  3. J. Bhasker, Rakesh Chadha
    Pages 15-42
  4. J. Bhasker, Rakesh Chadha
    Pages 43-100
  5. J. Bhasker, Rakesh Chadha
    Pages 101-121
  6. J. Bhasker, Rakesh Chadha
    Pages 123-146
  7. J. Bhasker, Rakesh Chadha
    Pages 147-177
  8. J. Bhasker, Rakesh Chadha
    Pages 179-225
  9. J. Bhasker, Rakesh Chadha
    Pages 227-316
  10. J. Bhasker, Rakesh Chadha
    Pages 317-363
  11. J. Bhasker, Rakesh Chadha
    Pages 365-446
  12. Back Matter
    Pages 447-572

About this book

Introduction

Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats.

This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful.

Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.

Keywords

CMOS Cell Library Crosstalk Parasitics STA Concepts Standard Timing layout logic modeling semiconductor verification

Authors and affiliations

  • Rakesh Chadha
  • J. Bhasker
  1. 1.eSilicon CorporationNew ProvidenceU.S.A.
  2. 2.eSilicon CorporationAllentownU.S.A.

Bibliographic information

  • DOI https://doi.org/10.1007/978-0-387-93820-2
  • Copyright Information Springer-Verlag US 2009
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-0-387-93819-6
  • Online ISBN 978-0-387-93820-2
  • About this book