Wafer Level 3-D ICs Process Technology

  • Chuan Seng Tan
  • Ronald J. Gutmann
  • L. Rafael Reif

Part of the Integrated Circuits and Systems book series (ICIR)

Table of contents

  1. Front Matter
    Pages 1-14
  2. Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif
    Pages 1-11
  3. Christopher Petti, S. Brad Herner, Andrew Walker
    Pages 1-17
  4. Mansun Chan
    Pages 1-17
  5. Sharath Hosali, Greg Smith, Larry Smith, Susan Vitkavage, Sitaram Arkalgud
    Pages 1-32
  6. Kuan-Neng Chen, Chuan Seng Tan, Andy Fan, L. Rafael Reif
    Pages 1-14
  7. A. Munding, H. Hübner, A. Kaiser, S. Penka, P. Benkart, E. Kohn
    Pages 1-39
  8. James Burns, Brian Aull, Robert Berger, Nisha Checka, Chang-Lee Chen, Chenson Chen et al.
    Pages 1-26
  9. Anna W. Topol, Steven J. Koester, Douglas C. La Tulipe, Albert M. Young
    Pages 1-21
  10. Jian-Qiang Lu, Timothy S. Cale, Ronald J. Gutmann
    Pages 1-38
  11. Bart Swinnen, Anne Jourdain, Piet De Moor, Eric Beyne
    Pages 1-11
  12. Robert S. Patti
    Pages 1-23
  13. Sheng-Chih Lin, Kaustav Banerjee
    Pages 1-26
  14. Scott K. Pozder, Robert E. Jones
    Pages 1-20
  15. Back Matter
    Pages 1-7

About this book


Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.

Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.


Applications enabled by 3-D integration CMOS Diffusion Technologie Three-dimensional (3-D) integration Through Silicon vias (TSVs) Wafer Wafer bonding Wafer-Level 3-D Technology Platforms circuit design integrated circuit silicon technology three dimensional integrated circuit

Editors and affiliations

  • Chuan Seng Tan
    • 1
  • Ronald J. Gutmann
    • 2
  • L. Rafael Reif
    • 3
  1. 1.School Electrical & Electronic Eng., Photonics Res. CentreNanyang Technological UniversitySingaporeSingapore
  2. 2.Center for Integrated ElectronicsRensselaer Polytechnic InstituteTroyU.S.A.
  3. 3.Dept. Electrical EngineeringMassachusetts Institute of TechnologyCambridgeU.S.A.

Bibliographic information

  • DOI
  • Copyright Information Springer Science+Business Media, LLC 2008
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering Engineering (R0)
  • Print ISBN 978-0-387-76532-7
  • Online ISBN 978-0-387-76534-1
  • Series Print ISSN 1558-9412
  • Buy this book on publisher's site