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The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits

The semi-empirical and compact model approaches

  • Paul┬áJespers

Part of the Analog Circuits and Signal Processing book series (ACSP)

Table of contents

  1. Front Matter
    Pages i-xvi
  2. Paul G. A. Jespers
    Pages 1-9
  3. Paul G. A. Jespers
    Pages 11-24
  4. Paul G. A. Jespers
    Pages 41-66
  5. Paul G. A. Jespers
    Pages 67-91
  6. Paul G. A. Jespers
    Pages 93-112
  7. Paul G. A. Jespers
    Pages 113-119
  8. Paul G. A. Jespers
    Pages 121-142
  9. Back Matter
    Pages 143-171

About this book

Introduction

How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.

Keywords

CMOS ROM Transistor integrated circuit large signal compact models low-voltage, low-power analog CMOS circuits micro-alloy transistor parameter acquisition sizing methodology static-induction transistor

Authors and affiliations

  • Paul┬áJespers
    • 1
  1. 1.TervurenBelgium

Bibliographic information

  • DOI https://doi.org/10.1007/978-0-387-47101-3
  • Copyright Information Springer-Verlag US 2010
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-0-387-47100-6
  • Online ISBN 978-0-387-47101-3
  • Buy this book on publisher's site