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VLSI: Systems on a Chip

IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI ’99) December 1–4, 1999, Lisboa, Portugal

  • Book
  • © 2000

Overview

Editors:
  1. Luis Miguel Silveira

    1. Systems and Computers Research Institute (INESC) and Cadence Europeans Laboratories (CEL), Dept. of Electrical and Computer Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon, Lisbon, Portugal

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  2. Srinivas Devadas

    1. Laboratory for Computer Science, Dept. of Elect. Eng. and Comp. Science, Massachusetts Institute of Technology, Cambridge, USA

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  3. Ricardo Reis

    1. Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

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Part of the book series: IFIP Advances in Information and Communication Technology (IFIPAICT, volume 34)

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Table of contents (57 chapters)

  1. Front Matter

    Pages i-xviii
    Download chapter PDF

  2. Optimizing Mixer Noise Performance: a 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application

    • Shenggao Li, Yue Wu, Chunlei Shi, Mohammed Ismail
    Pages 1-10

  3. An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices

    • Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Mark A. Hemming, Peter Holzmann, Oliver C. Kao et al.
    Pages 11-22

  4. A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process

    • Bingxin Li, Hannu Tenhunen
    Pages 23-34

  5. A Low Power CMOS Micromixer for GHz Wireless Applications

    • Yue Wu, Shenggao Li, Mohammed Ismail, Håkan Olsson
    Pages 35-46

  6. High Current, Low Voltage Current Mirrors and Applications

    • S. S. Rajput, S. S. Jamuar
    Pages 47-60

  7. Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications

    • Yue Wu, Hong-sun Kim, Fredrik Jonsson, Mohammed Ismail, Håkan Olsson
    Pages 61-68

  8. A Fast Parametric Model for Contact-Substrate Coupling

    • N. Masoumi, M. I. Elmasry, S. Safavi-Naeini
    Pages 69-76

  9. A Feature Associative Processor for Image Recognition Based on a A-D Merged Architecture

    • Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi et al.
    Pages 77-88

  10. Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications

    • A. M. Rassau, G. Alagoda, D. Lucas, J. Austin-Crowe, K. Eshraghian
    Pages 89-100

  11. Implementation of a Wavelet Transform Architecture for Image Processing

    • Camille Diou, Lionel Torres, Michel Robert
    Pages 101-112

  12. Scalable Run Time Reconfigurable Architecture

    • Abdellah Touhafi, Wouter Brissinck, Erik Dirkx
    Pages 113-124

  13. Frontier: A Fast Placement System for FPGAS

    • Russell Tessier
    Pages 125-136

  14. Dynamically Reconfigurable Implementation of Control Circuits

    • Nuno Lau, Valery Sklyarov
    Pages 137-148

  15. An IEEE Compliant Floating Point MAF

    • R. V. K. Pillai, D. Al-Khalili, A. J. Al-Khalili
    Pages 149-160

  16. Design and Analysis of On-Chip CPU Pipelined Caches

    • C. Ninos, H. T. Vergos, D. Nikolos
    Pages 161-172

  17. Synchronous to Asynchronous Conversion

    • J. Alcântara, S. Salomão, E. Granja, V. Alves, F. França
    Pages 173-180

  18. Clock Distribution Strategy for IP-based Development

    • Rui L. Aguiar, Dinis M. Santos
    Pages 181-191

  19. An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures

    • David H. Albonesi
    Pages 192-205

  20. Single Ended Pass-Transistor Logic

    • Mihai Munteanu, Peter A. Ivey, Luke Seed, Marios Psilogeorgopoulos, Neil Powell, Istvan Bogdan
    Pages 206-217
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Keywords

About this book

For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.

Editors and Affiliations

  • Systems and Computers Research Institute (INESC) and Cadence Europeans Laboratories (CEL), Dept. of Electrical and Computer Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon, Lisbon, Portugal

    Luis Miguel Silveira

  • Laboratory for Computer Science, Dept. of Elect. Eng. and Comp. Science, Massachusetts Institute of Technology, Cambridge, USA

    Srinivas Devadas

  • Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

    Ricardo Reis

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