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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings

  • Conference proceedings
  • © 2006

Overview

Editors:
  1. Johan Vounckx

    1. IMEC, Heverlee, Belgium

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  2. Nadine Azemard

    1. LIRMM, UMR CNRS/Université de Montpellier II, (C5506), Montpellier, France

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  3. Philippe Maurine

    1. University of Montpellier / LIRMM, II, Montpellier, France

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4148)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: PATMOS 2006.

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Table of contents (70 papers)

  1. Session 6 – Low Power Techniques

    1. Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters

      • Th. Giannopoulos, V. Paliouras
      Pages 203-213

    2. Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

      • A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii et al.
      Pages 214-224

    3. A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation

      • Toshiro Akino, Takashi Hamahata
      Pages 225-236

    4. Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique

      • B. Chung, J. B. Kuo
      Pages 237-246

  2. Session 7 – Applications and SoC Design

    1. Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators

      • Tiago Dias, Nuno Roma, Leonel Sousa
      Pages 247-255

    2. Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache

      • Gurhan Kucuk, Can Basaran
      Pages 256-266

    3. A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus

      • Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
      Pages 267-279

    4. Methodology for Dynamic Power Verification of Contactless Smartcards

      • Julien Mercier, Christian Dufaza, Mathieu Lisart
      Pages 280-291

    5. New Battery Status Checking Method for Implantable Biomedical Applications

      • Jong-pil Son, Kyu-young Kim, Ji-yong Jeong, Yogendera Kumar, Soo-won Kim
      Pages 292-300

  3. Session 8 – Modeling

    1. Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis

      • Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel
      Pages 301-310

    2. A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique

      • Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
      Pages 311-318

    3. Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow

      • Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson
      Pages 319-328

    4. Receiver Modeling for Static Functional Crosstalk Analysis

      • Mini Nanua, David Blaauw
      Pages 329-339

    5. Modeling of Crosstalk Fault in Defective Interconnects

      • Ajoy K. Palit, Kishore K. Duganapalli, Walter Anheier
      Pages 340-349

  4. Session 9 – Digital Circuits

    1. Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits

      • Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim
      Pages 350-359

    2. Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations

      • Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija
      Pages 360-369

    3. IR-drop Reduction Through Combinational Circuit Partitioning

      • Hai Lin, Yu Wang, Rong Luo, Huazhong Yang, Hui Wang
      Pages 370-381

    4. Low-Power Register File Based on Adiabatic Logic Circuits

      • Jianping Hu, Hong Li, Yangbo Wu
      Pages 382-392

    5. High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI

      • Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada et al.
      Pages 393-402

  5. Session 10 – Reconfigurable and Programmable Devices

    1. Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources

      • Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
      Pages 403-414
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  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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About this book

Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

Editors and Affiliations

  • IMEC, Heverlee, Belgium

    Johan Vounckx

  • LIRMM, UMR CNRS/Université de Montpellier II, (C5506), Montpellier, France

    Nadine Azemard

  • University of Montpellier / LIRMM, II, Montpellier, France

    Philippe Maurine

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