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Correct Hardware Design and Verification Methods

13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings

  • Conference proceedings
  • © 2005

Overview

Editors:
  1. Dominique Borrione

    1. TIMA Laboratory, VDS Group, Grenoble, France

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    You can also search for this editor in PubMed   Google Scholar

  2. Wolfgang Paul

    1. Computer Science Dept., Saarland University, Saarbrücken, Germany

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3725)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: CHARME 2005.

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Table of contents (42 papers)

  1. Evaluation of SAT-Based Tools

    1. An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment

      • Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P. Kurshan, Kenneth L. McMillan
      Pages 254-268

  2. Model Reduction

    1. Exploiting Constraints in Transformation-Based Verification

      • Hari Mony, Jason Baumgartner, Adnan Aziz
      Pages 269-284

    2. Identification and Counter Abstraction for Full Virtual Symmetry

      • Ou Wei, Arie Gurfinkel, Marsha Chechik
      Pages 285-300

  3. Verification of Memory Hierarchy Mechanisms

    1. On the Verification of Memory Management Mechanisms

      • Iakov Dalinger, Mark Hillebrand, Wolfgang Paul
      Pages 301-316

    2. Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification

      • Sudhindra Pandav, Konrad Slind, Ganesh Gopalakrishnan
      Pages 317-331

  4. Short Papers

    1. Symbolic Partial Order Reduction for Rule Based Transition Systems

      • Ritwik Bhattacharya, Steven German, Ganesh Gopalakrishnan
      Pages 332-335

    2. Verifying Timing Behavior by Abstract Interpretation of Executable Code

      • Christian Ferdinand, Reinhold Heckmann
      Pages 336-339

    3. Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths

      • Masahiro Fujita
      Pages 340-344

    4. Deadlock Prevention in the Æthereal Protocol

      • Biniam Gebremichael, Frits Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Rădulescu
      Pages 345-348

    5. Acceleration of SAT-Based Iterative Property Checking

      • Daniel Große, Rolf Drechsler
      Pages 349-353

    6. Error Detection Using BMC in a Parallel Environment

      • Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle
      Pages 354-358

    7. Formal Verification of Synchronizers

      • Tsachy Kapschitz, Ran Ginosar
      Pages 359-362

    8. A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems

      • Panagiotis Manolios, Sudarshan K. Srinivasan
      Pages 363-366

    9. Improvements to the Implementation of Interpolant-Based Model Checking

      • João Marques-Silva
      Pages 367-370

    10. High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design

      • Petr Matoušek, Aleš Smrčka, Tomáš Vojnar
      Pages 371-375

    11. Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic

      • Katell Morin-Allory, David Cachera
      Pages 376-379

    12. Resolving Quartz Overloading

      • Oliver Pell, Wayne Luk
      Pages 380-383

    13. FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers

      • Mona Safar, M. Watheq El-Kharashi, Ashraf Salem
      Pages 384-387

    14. Predictive Reachability Using a Sample-Based Approach

      • Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David Dill, E. Allen Emerson
      Pages 388-392

    15. Minimizing Counterexample of ACTL Property

      • ShengYu Shen, Ying Qin, SiKun Li
      Pages 393-397
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  1. Correct Hardware Design and Verification Methods

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Editors and Affiliations

  • TIMA Laboratory, VDS Group, Grenoble, France

    Dominique Borrione

  • Computer Science Dept., Saarland University, Saarbrücken, Germany

    Wolfgang Paul

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