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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings

  • Conference proceedings
  • © 2005

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Editors:
  1. Vassilis Paliouras

    1. Electrical and Computer Engineering Department, University of Patras, Greece

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  2. Johan Vounckx

    1. IMEC, Heverlee, Belgium

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    You can also search for this editor in PubMed   Google Scholar

  3. Diederik Verkest

    1. Dept. of Electrical Engineering, VUB, Brussels, Belgium

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3728)

Part of the book sub series: Programming and Software Engineering (LNPSE)

Included in the following conference series:

Conference proceedings info: PATMOS 2005.

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Table of contents (82 papers)

  1. Session 5: Low-Power Circuits

    1. An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits

      • Josep Rius, José Pineda, Maurice Meijer
      Pages 187-196

    2. Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques

      • Jean-Félix Perotto, Stefan Cserveny
      Pages 197-206

    3. Power Consumption in Reversible Logic Addressed by a Ramp Voltage

      • Alexis De Vos, Yvan Van Rentergem
      Pages 207-216

    4. Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing

      • Yuanlin Lu, Vishwani D. Agrawal
      Pages 217-226

    5. Back Annotation in High Speed Asynchronous Design

      • Pankaj Golani, Peter A. Beerel
      Pages 227-236

  2. Session 6: System-on-Chip Design

    1. Optimization of Reliability and Power Consumption in Systems on a Chip

      • Tajana Simunic, Kresimir Mihic, Giovanni De Micheli
      Pages 237-246

    2. Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs

      • Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
      Pages 247-256

    3. A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design

      • Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
      Pages 257-266

    4. Power Supply Selective Mapping for Accurate Timing Analysis

      • Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
      Pages 267-276

  3. Session 7: Busses and Interconnections

    1. Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses

      • Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
      Pages 277-285

    2. PSK Signalling on NoC Buses

      • Crescenzo D’Alessandro, Delong Shang, Alex Bystrov, Alex Yakovlev
      Pages 286-296

    3. Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding

      • Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
      Pages 297-307

    4. Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing

      • Giorgos Dimitrakopoulos, Dimitris Nikolos
      Pages 308-317

    5. Efficient Simulation of Power/Ground Networks with Package and Vias

      • Jin Shi, Yici Cai, Xianlong Hong, Shelton X. D. Tan
      Pages 318-328

  4. Session 8: Modeling

    1. Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation

      • Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo
      Pages 329-336

    2. Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates

      • Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz de Clavijo, David Guerrero Martos, E. Ostúa et al.
      Pages 337-347

    3. Compact Static Power Model of Complex CMOS Gates

      • Jose L. Rosselló, Sebastià Bota, Jaume Segura
      Pages 348-354

    4. Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model

      • Massimo Alioto, Gaetano Palumbo, Massimo Poli
      Pages 355-363

    5. Statistical Critical Path Analysis Considering Correlations

      • Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
      Pages 364-373

  5. Session 9: Design Automation

    1. A CAD Platform for Sensor Interfaces in Low-Power Applications

      • Didier Van Reeth, Georges Gielen
      Pages 374-381
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  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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About this book

Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof.

Editors and Affiliations

  • Electrical and Computer Engineering Department, University of Patras, Greece

    Vassilis Paliouras

  • IMEC, Heverlee, Belgium

    Johan Vounckx

  • Dept. of Electrical Engineering, VUB, Brussels, Belgium

    Diederik Verkest

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