Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

  • Tim Kogel
  • Rainer Leupers
  • Heinrich Meyr

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Pages 1-7
  3. Pages 43-58
  4. Pages 59-77
  5. Pages 79-112
  6. Pages 141-152
  7. Pages 153-157
  8. Back Matter
    Pages 159-199

About this book

Introduction

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

Keywords

Augmented Reality Electronic System Level (ESL) Multi-Processor System-on-Chip (MP-SoC) Network-on-Chip (NoC) Performance Processing QoS Simulation SystemC Transaction Level Modeling (TLM) architecture model modeling organization system on chip (SoC)

Authors and affiliations

  • Tim Kogel
    • 1
  • Rainer Leupers
    • 2
  • Heinrich Meyr
    • 2
  1. 1.CoWareGermany
  2. 2.RWTHGermany

Bibliographic information

  • DOI https://doi.org/10.1007/1-4020-4826-2
  • Copyright Information Springer 2006
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-4825-8
  • Online ISBN 978-1-4020-4826-5