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Fast, Efficient and Predictable Memory Accesses

Optimization Algorithms for Memory Architecture Aware Compilation

  • Lars Wehmeyer
  • Peter Marwedel

Table of contents

  1. Front Matter
    Pages i-xi
  2. Pages 1-2
  3. Pages 3-14
  4. Pages 15-88
  5. Pages 233-238
  6. Pages 239-241
  7. Back Matter
    Pages 243-257

About this book

Introduction

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

Keywords

Compiler DRAM Energy Memory RAM Timing Predictability embedded systems processor

Authors and affiliations

  • Lars Wehmeyer
    • 1
  • Peter Marwedel
    • 2
  1. 1.University of DortmundGermany
  2. 2.University of DortmundGermany

Bibliographic information

  • DOI https://doi.org/10.1007/1-4020-4822-X
  • Copyright Information Springer 2006
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-4821-0
  • Online ISBN 978-1-4020-4822-7
  • Buy this book on publisher's site