Routing Congestion in VLSI Circuits: Estimation and Optimization

  • Prashant Saxena
  • Rupesh S. Shelar
  • Sachin S. Sapatnekar

Part of the Series on Integrated Circuits and Systems book series (ICIR)

Table of contents

  1. Front Matter
    Pages i-xiv
  2. The Origins of Congestion

    1. Front Matter
      Pages 1-1
  3. The Estimation of Congestion

  4. The Optimization of Congestion

  5. Back Matter
    Pages 237-248

About this book


With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.

Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.

Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.


Computer-Aided Design (CAD) Routing Sapatnekar VLSI VLSI circuits estimation integrated circuit metrics optimization routing congestion

Authors and affiliations

  • Prashant Saxena
    • 1
  • Rupesh S. Shelar
    • 2
  • Sachin S. Sapatnekar
    • 3
  1. 1.Synopsys, Inc.HillsboroUSA
  2. 2.Intel CorporationHillsboroUSA
  3. 3.University of MinnesotaMinneapolisUSA

Bibliographic information

  • DOI
  • Copyright Information Springer Science+Business Media, LLC 2007
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering Engineering (R0)
  • Print ISBN 978-0-387-30037-5
  • Online ISBN 978-0-387-48550-8
  • Series Print ISSN 1558-9412
  • Buy this book on publisher's site