Leakage in Nanometer CMOS Technologies

  • Siva G. Narendra
  • Anantha Chandrakasan

Part of the Series on Integrated Circuits and Systems book series (ICIR)

Table of contents

  1. Front Matter
    Pages i-x
  2. Siva Narendra, Yibin Ye, Shekar Borkar, Vivek De, Anantha Chandrakasan
    Pages 21-39
  3. Benton Calhoun, James Kao, Anantha Chandrakasan
    Pages 41-75
  4. Kimiyoshi Usami, Takayasu Sakurai
    Pages 77-104
  5. Tadahiro Kuroda, Takayasu Sakurai
    Pages 105-140
  6. Siva Narendra, James Tschanz, James Kao, Shekar Borkar, Anantha Chandrakasan, Vivek De
    Pages 141-162
  7. Takayuki Kawahara, Kiyoo Itoh
    Pages 163-199
  8. Siva Narendra, James Tschanz, Shekar Borkar, Vivek De
    Pages 201-209
  9. Ali Keshavarzi, Kaushik Roy
    Pages 211-233
  10. Masayuki Miyazaki, Hiroyuki Mizuno, Takayuki Kawahara
    Pages 235-255
  11. Sagar Suthram, Siva Narendra, Scott Thompson
    Pages 281-299
  12. Back Matter
    Pages 301-307

About this book


Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers.


CMOS architecture microprocessor testing transistor

Authors and affiliations

  • Siva G. Narendra
    • 1
  • Anantha Chandrakasan
    • 2
  1. 1.Tyfone, Inc.USA
  2. 2.Massachusetts Institute of TechnologyUSA

Bibliographic information

  • DOI
  • Copyright Information Springer Science+Business Media, Inc. 2006
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-0-387-25737-2
  • Online ISBN 978-0-387-28133-9
  • Series Print ISSN 1558-9412
  • Buy this book on publisher's site