The readout board is discussed in detail in this section. As already mentioned, the board processes the incoming signals from detectors and generates a histogram. The PC can read the histogram from the readout board with a web browser.
This board consists of a main and a daughter board, which is 35×160×160 mm in size and weighs 420 g. Figure 3 shows photographs of these boards. The daughter board, mounted on the main board, is a connector adapter so as to allow the use of various types of connectors. The signals are processed by the main board, and the main parts of this board are comparators, a field programmable gate array (FPGA, Xilinx Spartan3AN-700; XILINX, 2007), and an Ethernet physical layer device (PHY, SMSC LAN8700i; SMSC, 2007).
Figure 4 shows a block diagram of the readout board that consists of NIM connectors, comparators, an event filter, a histogram generator, a network processor, and an Ethernet PHY. The FPGA works on a 50-MHz system clock. The event filter, the histogram generator, and the network processor are implemented on the single FPGA.
The detector signals are received by the comparators and are digitized after they have been compared with threshold voltages. The event filter selects candidate muon events for which the muon path can be constructed and generates information data on the paths. The data consist of a detection time and detection positions of the two counters. A histogram that depicts the angular distribution of the selected events is generated by the histogram generator using the path information. The network processor handles network protocols (Stevens, 1994) to access the histogram from a remote PC using a web browser. The network protocols used for this purpose are Ethernet, Internet Protocol (IP), Transmission Control Protocol (TCP), Hyper Text Transfer Protocol (HTTP), and Hyper Text Markup Language (HTML). The Ethernet PHY converts signals to meet Ethernet specifications. The FPGA circuits are discussing in more detail in the following sections.
3.1 Event filter
The event filter selects events that can be used to construct the muon paths and generates path information.
Figure 5 shows a block diagram of the event filter which consists of samplers and a coincidence unit. Input signals from the comparators are sampled at 200 MHz (period 5 ns). The sampled signal is stretched to 40 ns when the pulse width is shorter than 40 ns in order to be in synchronization with the system clock. The coincidence unit selects events from the sampled signals and generates the information on the candidate muon path. The selection criteria are as follows: there is one signal from each scintillator-array plane, the two signals of the counter are detected simultaneously, and the four signals are in a coincidence window. The window size can be set from 0 to 2 s in steps of 20 ns. An angle of the incident muon is calculated using the difference between detection positions of two counters. The path information consists of two 5-bit-width data sets containing the detection position differences for horizontal and vertical scintillating strips, respectively.
3.2 Histogram generator
The histogram is generated in a 32-bit-width internal memory of the FPGA. The path information, 10 bit in width and generated by the coincidence unit, is used as the address for access to the internal memory. The data according to the address are counted up when an event is detected. These data are read by the network processor described in the next section, using a remote PC.
3.3 Network processor
The network processor handles the network protocols used to access the histogram from a remote PC using a web browser. The PC can execute instructions as follows: obtain and clear histogram data, and obtain and clear data of event counters for monitor of the detectors.
The feature of this block is that those network protocols are processed by only a hardware circuit specialized for a web page. There is no CPU and no other programmable sequencers in this block. This design has advantages in terms of power consumption and operating failure rate. The protocols are generally processed by a system employing an embedded CPU with an operating system (OS). The system requires an external memory device because the size of the internal memories is too small to store a program. The use of a small number of devices contributes to a reduced power consumption and failure rate while running.
Figure 6 shows a block diagram of the network processor, which consists of a TCP/IP processor (SiTCP) (Uchida and Tanaka, 2006; Uchida, 2008), a HTTP/HTML parser, event counters, a read only memory (ROM), a multiplexer (MUX), and a data generator. This board works as a web server. The network protocols processed by this block are HTML, HTTP, TCP, IP, and Ethernet. The SiTCP, which is a hardware-based TCP/IP processor that can be implemented on a FPGA with no other external devices (such as memory devices; Uchida and Tanaka, 2006; Uchida, 2008), processes TCP, IP, and Ethernet. The parser analyzes HTML and HTTP data extracted from the TCP packets by the SiTCP and executes commands from the remote PC. There are three commands—clear histogram data; clear event counters; obtain histogram data. There are distinct buttons for the histogram data and event counters on a web page (see Fig. 7). A command packet to clear histogram data or event counters is transmitted from the PC when the clear button is clicked. Acknowledge packets for the commands are replied to by this block when the histogram data or the event counters are cleared. To measure the counting rate of the detectors, the event counters total the detector signals for 1 s after the clear command is received.
Figure 8 shows a HTML source file of the web page, which consists of three parts—fixed data; histogram data; values of event counters. The fixed data are a HTML header, HTML codes, and Java scripts. The Java scripts are used to reduce the load of this board. The fixed data are read from the ROM, and the histogram data and values of event counters are read from the histogram memory and event counters, respectively. These data are selected by the data generator with the MUX when data for the web page are generated. The selected data are forwarded to the SiTCP and transmitted to a PC. The histogram is displayed as a web page on the remote PC finally.