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Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

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We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V th, channel length L and gate oxide thickness t ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.

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  1. K. A. Bowman, S. G. Duvall, J. D. Meindl, “Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE J. Solid-State Circuits 37, No. 2, 183 (Feb. 2002), DOI: 10.1109/4.982424.

    Article  Google Scholar 

  2. Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek De, “Parameter variations and impact on circuits and microarchitecture,” in Proc. of 40th Annual Design Automation Conf., DAC (2003), pp. 338–342, DOI: 10.1145/775832.775920.

    Google Scholar 

  3. T. Karnik, V. De, S. Borkar, “Statistical design for variation tolerance: key to continued Moore’s law,” in Proc. of Int. Conf. on Integrated Circuit Design and Technology, ICICDT’04 (2004), pp. 175–176, DOI: 10.1109/ICICDT.2004.1309939.

    Google Scholar 

  4. Bin Yu, Haihong Wang, A. Joshi, Qi Xiang, Effiong Ibok, Ming-Ren Lin, “15 nm gate length planar CMOS transistor,” Electron Devices Meeting: Int. Tech. Dig., IEDM’01, 2–5 Dec. 2001, Washington, DC, USA (Washington, 2001), pp. 11.7.1–11.7.3, DOI: 10.1109/IEDM.2001.979669.

    Google Scholar 

  5. D. Hisamoto, Wen-Chin Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, Erik Anderson, Tsu-Jae King, J. Bokor, Chenming Hu, “FinFET—a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices 47, No. 12, 2320 (Dec. 2000), DOI: 10.1109/16.887014.

    Article  Google Scholar 

  6. J. Y. S. Balasubramanium, “Design of sub-50 nm FinFET based low power SRAMs,” Semicond. Sci. Technol. 23, 13 (2008).

    Google Scholar 

  7. K. Zhang, U. Bhattacharya, Zhanping Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Yih Wang, Bo Zheng, M. Bohr, “A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply,” IEEE J. Solid-State Circuits 41, No. 1, 146 (2005), DOI: 10.1109/JSSC.2005.859025.

    Article  Google Scholar 

  8. M. D. Powell, S.-H. Yang, B. Falsafi, K. Roy, T. N. Vijaykumar, “Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories,” in Proc. of 2000 Int. Symp. on Low Power Electronics and Design, ISLED’00 (July 2000), pp. 90–95, DOI: 10.1109/LPE.2000.155259.

    Google Scholar 

  9. Amit Agarwal, Hai Li, Kaushik Roy, “DRG-cache: a data retention gated-ground cache for low power,” in Proc. of 39th Design Automation Conf., June 2002 (2002), pp. 473–478, DOI: 10.1109/DAC.2002.1012671.

    Google Scholar 

  10. Rafik S. Guindi, Farid N. Najm, “Design techniques for gate-leakage reduction in CMOS circuits,” in Proc. of Fourth Int. Symp. on Quality Electronic Design, 24–26 March 2003 (2003), pp. 61–65, DOI: 10.1109/ISQED.2003.1194710.

    Google Scholar 

  11. L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, Lidija Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, W. Haensch, “Stable SRAM cell design for the 32 nm node and beyond,” in Proc. of Symp. on VLSI Technology: Digest of Tech. Papers, 14–16 June 2005 (Jun. 2005), pp. 128–129, DOI: 10.1109/.2005.1469239.

    Google Scholar 

  12. T. Enomoto, Y. Oka, H. Shikano, T. Harada, “A self-controllable voltage-level (SVL) circuit for low-power high-speed CMOS circuits,” in Proc. of 28th European Conf. on Solid-State Circuits, ESSCIRC 2002, 24–26 Sept. 2002, Florence, Italy (2002), pp. 411–414.

    Google Scholar 

  13. K. Kanda, H. Sadaaki, T. Sakurai, “90% write power-saving SRAM using sense-amplifying memory cell,” IEEE J. Solid-State Circuits 39, No. 6, 927 (June 2004), DOI: 10.1109/JSSC.2004.827793.

    Article  Google Scholar 

  14. S. Lavanya, J. Lisbin, “Self controllable voltage level (SVL) for low power consumption,” in Proc. of IE Int. Conf. on Computational Intelligence & Computing Research, ICCIC, 18–20 Dec. 2012, Coimbatore (IEEE, 2012), pp. 1–5, DOI: 10.1109/ICCIC.2012.6510228.

    Google Scholar 

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Correspondence to Ravindra Singh Kushwah.

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Original Russian Text © R.S. Kushwah, S. Akashe, 2014, published in Izv. Vyssh. Uchebn. Zaved., Radioelektron., 2014, Vol. 57, No. 9, pp. 3–17.

This work was supported by ITM University (Gwalior) in collaboration with Cadence System Design (Bangalore).

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Kushwah, R.S., Akashe, S. Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells. Radioelectron.Commun.Syst. 57, 383–393 (2014).

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