Automatic Control and Computer Sciences

, Volume 52, Issue 1, pp 1–12 | Cite as

Two-Modulus Codes with Summation of On-Data Bits for Technical Diagnostics of Discrete Systems

  • D. V. Efanov
  • V. V. Sapozhnikov
  • Vl. V. Sapozhnikov


A fundamentally new approach to building a code with summation of on-data bits based on the selection and separate check of subsets of bits of the data vector is presented. The properties of the proposed code are analyzed in comparison with the classic and modified Berger codes. The advantages and disadvantages of new codes with summation of on-data bits are noted. The basic properties of the proposed codes with summation that should be taken into account in solving problems of technical diagnostics are established. The results of experimental applications of the developed codes to the organization of concurrent error detection systems of combinational benchmarks from LGSynth`89 are given.


technical diagnostics concurrent error detection system code with summation of on-data bits Berger code modified Berger code two-modulus sum code error detection features undetectable error structural redundancy 


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  1. 1.
    McCluskey, E.J., Logic Design Principles (with Emphasis on Testable Semicustom Circuits), New Jersey: Prentice-Hall, 1986.Google Scholar
  2. 2.
    Lala, P.K., Principles of Modern Digital Design, New Jersey: John Wiley & Sons, 2007.CrossRefGoogle Scholar
  3. 3.
    Sogomonyan, E.S. and Slabakov, E.V., Samoproveryaemye ustroistva i otkazoustoichivye sistemy (Self-Testing Devices and Fault-Tolerant Systems), Moscow: Radio i Svyaz’, 1989.Google Scholar
  4. 4.
    Piestrak, S.J., Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wroclaw: Oficyna Wydawnicza Politechniki Wroclavskiej, 1995.Google Scholar
  5. 5.
    Fujiwara, E., Code Design for Dependable Systems: Theory and Practical Applications, John Wiley & Sons, 2006.CrossRefzbMATHGoogle Scholar
  6. 6.
    Sapozhnikov, V.V. and Sapozhnikov, Vl.V., Samoproveryaemye diskretnye ustroistva (Self-Checking Discrete Devices), St. Petersburg: Energoatomizdat, 1992.Google Scholar
  7. 7.
    Carter, W. and Schneider, P., Design of dynamically checked computers, Proceedings of IFIP Congress 68, Edinburgh, 1968, pp. 878–883.Google Scholar
  8. 8.
    Goessel, M. and Graf, S., Error Detection Circuits, London: McGraw-Hill, 1994.Google Scholar
  9. 9.
    Drozd, A.V., An unconventional view of working diagnostics of computing devices, Probl. Upr., 2008, no. 2, pp. 48–56.Google Scholar
  10. 10.
    Nicolaidis, M. and Zorian, Y., On-line testing for VLSI—a compendium of approaches, J. Electron. Test.: Theory Appl., 1998, vol. 12, pp. 7–20.CrossRefGoogle Scholar
  11. 11.
    Das, D. and Touba, N.A., Synthesis of circuits with low-cost concurrent error detection based on Bose-Lin codes, J. Electron. Test.: Theory Appl., 1999, vol. 15, nos. 1–2, pp. 145–155.CrossRefGoogle Scholar
  12. 12.
    Das, D. and Touba, N.A., Weight-based codes and their application to concurrent error detection of multilevel circuits, Proceedings of 17th IEEE Test Symposium, USA, California, 1999, pp. 370–376.Google Scholar
  13. 13.
    Das, D., Touba, N.A., Seuring M., and Gossel, M., Low cost concurrent error detection based on modulo weight-based codes, Proceedings of IEEE 6th International On-Line Testing Workshop (IOLTW), Palma de Mallorca, 2000, pp. 171–176.Google Scholar
  14. 14.
    Mitra, S. and McCluskey, E.J., Which concurrent error detection scheme to choose?, Proceedings of International Test Conference, October 3–5, 2000, Atlantic City, NJ, 2000, pp. 985–994.Google Scholar
  15. 15.
    Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V., and Cherepanova, M.R., Modular codes with summation in concurrent error-detection systems. I. Properties of error detection by codes in data vectors, Elektron. Model., 2016, vol. 38, no. 2, pp. 27–48.Google Scholar
  16. 16.
    Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V., and Cherepanova, M.R., Modular codes with summation in concurrent error-detection systems. II. Reduction of structural redundancy of concurrent error-detection systems, Elektron. Model., 2016, vol. 38, no. 3, pp. 47–61.Google Scholar
  17. 17.
    Berger, J.M., A note on error detection codes for asymmetric channels, Inf. Control, 1961, vol. 4, no. 1, pp. 68–73.MathSciNetCrossRefzbMATHGoogle Scholar
  18. 18.
    Jha, N.K. and Vora, M.B., At-unidirectional errors-detecting systematic code, Comput. Math. Appl., 1988, vol. 16, no. 9, pp. 705–714.MathSciNetCrossRefzbMATHGoogle Scholar
  19. 19.
    Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., On summation code properties in functional control circuits, Autom. Remote Control, 2010, vol. 71, no. 6, pp. 1117–1123.MathSciNetCrossRefzbMATHGoogle Scholar
  20. 20.
    Parkhomenko, P.P. and Sogomonyan, E.S., Osnovy tekhnicheskoi diagnostiki (optimizatsiya algoritmov diagnostirovaniya, apparaturnye sredstva) (Basics of Technical Diagnostics (Optimization of Diagnostic Algorithms, Hardware Tools)), Moscow: Energoatomizdat, 1981.Google Scholar
  21. 21.
    Saposhnikov, V.V., Morosov, A., Saposhnikov, Vl.V., and Göessel, M., A new design method for self-checking unidirectional combinational circuits, J. Electron. Test.: Theory Appl., 1998, vol. 12, nos. 1–2, pp. 41–53.Google Scholar
  22. 22.
    Dong, H., Modified Berger codes for detection of unidirectional errors, Digest of Papers 12th Annual Symposium on Fault-Tolerant Computing, 1982, pp. 317–320.Google Scholar
  23. 23.
    Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., On codes with summation of data bits in concurrent error detection systems, Autom. Remote Control, 2014, vol. 75, no. 8, pp. 1460–1470.CrossRefzbMATHGoogle Scholar
  24. 24.
    Sapozhnikov, V., Sapozhnikov, Vl., Efanov, D., and Dmitriev, V., New sum code for effective detection of double errors in data vectors, Proceedings of 13th IEEE East-West Design & Test Symposium (EWDTS’2015), Batumi, 2015, pp. 154–159. doi 10.1109/EWDTS.2015.7493123Google Scholar
  25. 25.
    Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Construction of a modified Berger code with a minimum number of undetectable information bit errors, Elektron. Model., 2012, vol. 34, no. 6, pp. 17–29.Google Scholar
  26. 26.
    Efanov, D., Sapozhnikov, V., and Sapozhnikov, Vl., Generic two-modulus sum codes for technical diagnostics of discrete systems problems, Proceedings of 14th IEEE East-West Design & Test Symposium (EWDTS’2016), Yerevan, 2016, pp. 256–260.Google Scholar
  27. 27.
    Collection of Digital Design Benchmarks.].Google Scholar
  28. 28.
    Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K., and Sangiovanni-Vincentelli, A., SIS: A System for Sequential Circuit Synthesis, University of California, 1992.Google Scholar

Copyright information

© Allerton Press, Inc. 2018

Authors and Affiliations

  • D. V. Efanov
    • 1
  • V. V. Sapozhnikov
    • 1
  • Vl. V. Sapozhnikov
    • 1
  1. 1.Emperor Alexander I St. Petersburg State Transport UniversitySt. PetersburgRussia

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