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Area minimization of regular structures based on solving logical equations

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Abstract

The problem of area minimization of regular matrix structures in custom VLSI circuits using simple folding is considered. A method for solving the key simple folding issue, i.e., implementability testing of a folding set consisting of pairs of mutually foldable columns (rows), is proposed. It is shown how the problem of implementability analysis of the folding set may be reduced to solving a logical equation and the problem of finding roots of the equation to the known problem of satisfiability testing of a conjunctive normal form.

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References

  1. Ullman, J.D., Computational Aspects of VLSI Computer Science, 1984, Moscow Radio Svyaz’, 1990.

    Google Scholar 

  2. Biswas, N.N., Logic Design Theory, Prentice-Hall Int., 1993.

    Google Scholar 

  3. DeMicheli, G. and Sangiovanni-Vincentelli, A., Multiple constrained folding of programmable logic arrays, IEEE Trans. Computer-Aided Design, 1983, vol. 2, pp. 151–167.

    Article  Google Scholar 

  4. Devadas, S. and Newton, A.R., Topological optimization of multiple-level array logic, IEEE Trans. Computer-Aided Design, 1987, vol. 6, pp. 915–941.

    Article  Google Scholar 

  5. Macii, E. and Wolf, T., Graph models for PLA folding problems, Int. J. Syst. Sci., 1996, vol. 26, pp. 1439–1445.

    Article  Google Scholar 

  6. Lecky, J.E., Murphy, O.J., and Absher, R.G., Graph theoretic algorithms for the PLA folding problem, IEEE Trans. Computer-Aided Design, 1989, vol. 8, pp. 1014–1021.

    Article  Google Scholar 

  7. Cheremisinova, L.D., Some results in optimal PLA folding, Proc. 3d Int. Conf. on Computer-Aided Design of Dis-crete Devices (CAD DD-99), Minsk, 1999.

    Google Scholar 

  8. Cheremisinova, L.D., Minimization of custom-made VLSI regular matrix structure square, Informatika, 2004, no. 1, pp. 121–131.

    Google Scholar 

  9. Devadas, S., Optimal layout via boolean satisfiability, Proc. Int. Conf. on Computer-Aided Design (ICCAD-89), 1989, pp. 294–297.

    Google Scholar 

  10. Quintana, J.M., Avedillo, J.M., Parra, M.P., and Huertas, J.L., Optimum PLA folding through boolean satisfi-ability, Proc. Asian South Pacific Design Autom. Conf. (ASP DAC-95), pp. 289–293.

  11. Bryant, R.E., Graph-based algorithms for boolean function manipulation, IEEE Trans. Compt., 1986, vol. 35, pp. 677–691.

    Article  MATH  Google Scholar 

  12. Mahajan, Y., Fu, Z., and Malik, S., Zchaff 2004: An efficient SAT solver, in Theory and Applications of Satisfa-bility Testing (2004 SAT solver competition and QBF solver evaluation (invited papers)). Berlin Springer-Verlag, 2005.

    Google Scholar 

  13. Goldberg, E. and Novikov, Y., Berkmin: A fast and robust SAT-solver, Design, Autom, Test in Europe. 2002, pp. 142–149.

    Google Scholar 

  14. Eén, N. and Sörensson, N., Mini-SAT–http://www.cs.chalmers.se/Cs/Research/ FormalMethods/MiniSat

  15. Cheremisinova, L. and Novikov, D., SAT-based approach to verification of logical descriptions with functional indeterminacy, Proc. 8th Int. Workshop on Boolean Problems, Freiberg (Sachsen): 2008.

    Google Scholar 

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Authors and Affiliations

  1. United Institute of Informatics Problems, National Academy of Sciences of Belarus, ul. Surganova 6, Minsk, 220012, Belarus

    L. D. Cheremisinova

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  1. L. D. Cheremisinova
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Correspondence to L. D. Cheremisinova.

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Original Russian Text © L.D. Cheremisinova, 2015, published in Avtomatika i Vychislitel’naya Tekhnika, 2015, No. 4, pp. 28–38.

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Cheremisinova, L.D. Area minimization of regular structures based on solving logical equations. Aut. Control Comp. Sci. 49, 208–215 (2015). https://doi.org/10.3103/S0146411615040045

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