Skip to main content
SpringerLink
Log in

Realization of addition and multiplication operations in unitary codes

  • Published:
Automatic Control and Computer Sciences Aims and scope Submit manuscript

Abstract

This article discusses the implementation of the basic operations of modular arithmetic, addition and multiplication, for the case of data presentation in unitary codes. Analytical descriptions of the functions that are implemented at the outputs of the modular adder and the modular multiplier are proposed. We give logical schemes of the adder and multiplier by modulo three. These schemes are more efficient compared to their counterparts.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Dolgov, A.I., Diagnostika ustroystv, funksioniruyushih v sisteme ostatochnyh klassov (Diagnostic of Devices Operating in the Residue Number System), Moscow: Radio i Svyaz’, 1982.

    Google Scholar 

  2. Chervyakov, N.I., Sakhnyuk, P.A., Shaposhnikov, A.V., and Ryadnov, S.A., Modulyarnye parallelnye vychislitel’nye structury neyroprocessornyh sistem (Modular Parallel Computing Structures of Neuroprocessor Systems), Moscow: Fizmatlit, 2003.

    Google Scholar 

  3. Kornilov, A.I., Semenov, M.Yu., and Kalashnikov, V.S., Methods of Apparatus Optimization of Adders for Two Operands in the Residue Number System, Izv. Vyssh. Uchebn. Zaved., Elektronika, 2004, no. 1, pp. 75–82.

  4. Suprun, V.P., and Gorodecky, D.A., Synthesis of n-Operand Adders by Modulo 3, Avtom. Vych. Tekh., 2010, no. 3, pp. 72–80.

  5. Stempkovskii, A.L., Kornilov, A.I., and Semenov, M.Yu., Implementation Details of the Realization of Digital Signal Processing Devices in the Integrated Execution Using Modular Arithmetic, Inf. Tekhnol., 2004, no. 2, pp. 2–9.

  6. Suprun, V.P., and Gorodecky, D.A., The Method of Block-Structured Synthesis of Computing Devices of Modular Arithmetic, Informatika, 2009, no. 4 (24), pp. 74–79.

Download references

Author information

Authors and Affiliations

  1. Faculty of Mechanics and Mathematics, Belarusian State University, pr. Nezavisimosti 4, Minsk, 220030, Belarus

    V. P. Suprun & D. A. Gorodecky

Authors
  1. V. P. Suprun
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. D. A. Gorodecky
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to V. P. Suprun.

Additional information

Original Russian Text © V.P. Suprun, D.A. Gorodecky, 2010, published in Avtomatika i Vychislitel’naya Tekhnika, 2010, No. 5, pp. 59–71.

About this article

Cite this article

Suprun, V.P., Gorodecky, D.A. Realization of addition and multiplication operations in unitary codes. Aut. Conrol Comp. Sci. 44, 292–301 (2010). https://doi.org/10.3103/S014641161005007X

Download citation

  • Received:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.3103/S014641161005007X

Keywords

Search

Navigation