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Simulation and computation of the asymmetry of a clocked balanced tunnel-diode comparator

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Abstract

By means of simulation and computation, a clocked balanced tunnel-diode comparator, in which the clock signal conditioner is also a tunnel diode, is studied. Simulation and computation of the tunnel-diode asymmetry required for obtaining a minimum offset of the zero level of the compensation voltage are carried out. Simulation of the clocked balanced comparator is performed by means of the Tanner T-Spice program.

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Authors and Affiliations

  1. Institute of Electronics and Computer Science, Dzerbenes st. 14, Riga, LV-1006, Latvia

    E. Beiner & K. Krumin’sh

Authors
  1. E. Beiner
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  2. K. Krumin’sh
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Correspondence to E. Beiner.

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Original Russian Text © E. Beiner, K. Krumin’sh, 2009, published in Avtomatika i Vychislitel’naya Tekhnika, 2009, No. 2, pp. 76–82.

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Beiner, E., Krumin’sh, K. Simulation and computation of the asymmetry of a clocked balanced tunnel-diode comparator. Aut. Conrol Comp. Sci. 43, 109–112 (2009). https://doi.org/10.3103/S0146411609020084

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  • DOI: https://doi.org/10.3103/S0146411609020084

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