Radioelectronics and Communications Systems

, Volume 60, Issue 11, pp 512–518 | Cite as

Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology



A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3Vinterface.Anew level converter realized with +1.8Vdevices that can convert 0/1Vvoltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Yingyan Lin, Xuecheng Zou, Zhaoxiao Zheng, Wenjie Huo, Xiaofei Chen, Wenjing Kang, “High-speed, low switching noise and load adaptive output buffer,” Proc. of IEEE Int. Symp. on Integrated Circuits, ISIC, 14-16 Dec, 2009, Singapore (IEEE, 2009), pp. 280–282. URI: Scholar
  2. 2.
    R. S. Scott, N. A. Dumin, T. W. Hughes, D. J. Dumin, B. T. Moore, “Properties of high-voltage stress generated traps in thin silicon oxide,” IEEE Trans. Electron Devices 43, No. 7, 1133 (1996). DOI: 10.1109/16.502425.CrossRefGoogle Scholar
  3. 3.
    B. Mahendranath, A. Srinivasulu, “Analysis of two new voltage level converters with various load conditions,” Int. J. Advances Telecommunications, Electrotechnics, Signals and Systems 2, No. 3, 92 (2013). URI: Scholar
  4. 4.
    A. Srinivasulu and M. Rajesh, “ULPD and CPTL pull-up stages for differential cascode voltage switch logic,” J. Engineering 2013, Article ID 595296, 5 pages (2013). DOI: 10.1155/2013/595296.Google Scholar
  5. 5.
    A. B. T. Sundari and Avireni Srinivasulu, “High speed level converters with short circuit current reduction,” Int. J. Advances in Telecommunications, Electrotechnics, Signals and Systems 3, No. 2, 44 (2014). DOI: 10.11601/ijates.v3i2.92.Google Scholar
  6. 6.
    B. Mahendranath and Avireni Srinivasulu, “Performance analysis of a new CMOS output buffer,” Proc. of IEEE Int. Conf. on Circuits, Power and Computing Technologies, 20-21 Mar. 2013, Nagercoil, India (IEEE, 2013), pp. 752–755. DOI: 10.1109/ICCPCT.2013.6529041.Google Scholar
  7. 7.
    M. J. M. Pelgrom and E. C. Dijkmans, “A 3/5 V compatible I/O buffer,” IEEE J. Solid-State Circuits 30, No. 7, 823 (1995). DOI: 10.1109/4.391124.CrossRefGoogle Scholar
  8. 8.
    M.-D. Ker and C.-S. Tsai, “Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit,” Proc. of IEEE Int. Symp. on Circuits and Systems, 25-28 May 2003, Bangkok, Thailand (IEEE, 2003), Vol. 4, pp. 97–100. DOI: 10.1109/ISCAS.2003.1206197.Google Scholar
  9. 9.
    L. T. Clark, “A high-voltage output buffer fabricated on a 2V CMOS technology,” Proc. of Symp. on VLSI Circuits, 17-19 Jun 1999, Kyoto, Japan (IEEE, 1999), pp. 61–62. DOI: 10.1109/VLSIC.1999.797236.Google Scholar
  10. 10.
    Shih-Lun Chen and Ming-Dou Ker, “An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process,” IEEE Trans. Circuits and Systems II: Express Briefs 54, No. 1, 14 (2007). DOI: 10.1109/TCSII. 2006.883202.CrossRefGoogle Scholar
  11. 11.
    Chien-Cheng Yu, Wei-Ping Wang, Bin-Da Liu, “A new level converter for low-power applications,” Proc. of IEEE Int. Symp. on Circuits and Systems, 6-9 May 2001, Sydney, Australia (IEEE, 2001), Vol. 1, pp. 113-116. DOI: 10.1109/ISCAS.2001.921801.Google Scholar
  12. 12.
    N. Otsuka and M. A. Horowitz, “Circuit techniques for 1.5-V power supply flash memory,” IEEE J. Solid-State Circuits 32, No. 8, 1217 (1997). DOI: 10.1109/4.604078.CrossRefGoogle Scholar
  13. 13.
    Y. Kanno, H. Mizuno, K. Tanaka, and T. Watanabe, “Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs,” Proc. of Symp. on VLSI Circuits, 15-17 Jul. 2000, Honolulu, HI, USA (IEEE, 2000), pp. 202–203. DOI: 10.1109/VLSIC.2000.852890.Google Scholar
  14. 14.
    W.-T. Wang, M.-D. Ker, M.-C. Chiang, and C.-H. Chen, “Level shifters for high-speed 1 V to 3.3 Vinterfaces in a 0.13 μm Cu-interconnection/low-k CMOS technology,” Proc. of IEEE Int. Symp. on VLSI Technology, Systems and Applications, 18-20 Apr. 2001, Hsinchu, Taiwan (IEEE, 2001), pp. 307–310. DOI: 10.1109/ VTSA.2001.934546.Google Scholar
  15. 15.
    Ch. Ping-Yuan and Yu Chien-Cheng, “A voltage level converter circuit design with low power consumption,” Proc. of 6th IEEE Int. Conf. on ASIC, 24-27 Oct. 2005, Shanghai, China (IEEE, 2005), pp. 358–359. DOI: 10.1109/ICASIC.2005.1611324.Google Scholar

Copyright information

© Allerton Press, Inc. 2017

Authors and Affiliations

  1. 1.Vignan UniversityVadlamudiIndia
  2. 2.JECRC UniversityJaipurIndia

Personalised recommendations