Central European Journal of Computer Science

, Volume 2, Issue 2, pp 118–127

Using parallelization to improve the efficiency of an automated taxi route generation algorithm

Research Article

DOI: 10.2478/s13537-012-0012-x

Cite this article as:
Hall, A., Gabilondo, M. & Dechev, D. centr.eur.j.comp.sci. (2012) 2: 118. doi:10.2478/s13537-012-0012-x
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Abstract

As part of the Federal Aviation Administration’s (FAA) Next Generation Air Transportation System (NextGen) concept, surface support tools that generate taxi routes and monitor pilot conformance against those routes have been designed and implemented by Mosaic ATM and tested in simulations conducted by The Mitre Corporation’s Center for Advanced Aviation System Development(CAASD). The purpose of these tools is to increase the overall safety of the airport’s surface by detecting aircraft movement that is not in conformance with the taxi route assigned to that aircraft. Additionally, the tools aim to increase the overall efficiency of airport operations by ensuring that aircraft taxi in compliance with their assigned routes. One of the keys to providing a reliable conformance monitoring system is to produce reliable taxi routes against which to monitor compliance. The tools provided by Mosaic ATM generate these taxi routes via a set of predefined routes commonly used at an airport. In the simulations conducted by CAASD, it was found that the routes provided were found to be reliable and trustworthy. In addition to the predefined routes, Mosaic ATM provided an ad hoc route capability. This capability uses an algorithm that finds a route based on the taxiways assigned by a user through the ad hoc route tool. However, in the simulations conducted by CAASD, this tool was not used extensively by the users. In this paper, we describe our efforts to verify the correctness of the ad hoc taxi route generation algorithm as well as our efforts to increase the speed of the algorithm by implementing a lock-free parallelized version.

Keywords

surface automation taxi routing multi-core processing lock-free 

Copyright information

© Versita Warsaw and Springer-Verlag Wien 2012

Authors and Affiliations

  1. 1.University of Central FloridaOrlandoUSA
  2. 2.Scalable and Secure Systems R&D Department Sandia National LaboratoriesLivermoreUSA

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