Surface and interface properties of thin pentacene and parylene layers

Abstract

To improve Organic Thin Film Transistor (OTFT) properties we study OTFT semiconductor/dielectric interfacial properties via examination of the gate dielectric using thin Parylene C layer. Structural and morphology properties of pentacene layers deposited on parylene layer and SiO₂/Si substrate structure were compared. The surface morphology was investigated using atomic force microscopy (AFM) and scanning electron microscopy (SEM). AFM topography of pentacene layer in non-contact mode confirmed the preferable pentacene grain formation on parylene surface in dependence on layer thickness. The distribution of chemical species on the surfaces and composition depth profiles were measured by secondary ion mass spectroscopy (SIMS) and surface imaging. The depth profiles of the analyzed structures show a homogenous pentacene layer, characterized with C or C₂ ions. Relatively sharp interface between pentacene and parylene layers was estimated by characteristic increased intensity of CCl ions peak. For revealing the pentacene phases in the structures the Micro-Raman spectroscopy was utilized. Conformal coatings of parylene and pentacene layers without pinholes resulted from the deposition process as was confirmed by SIMS surface imaging. For the pentacene layers thicker than 20 nm, both thin and bulk pentacene phases were detected by Micro-Raman spectroscopy, while for the pentacene layer thickness of 5 and 10 nm the preferable thin phase was detected. The complete characterisation of pentacene layers deposited on SiO₂ and parylene surface revealed that the formation of large grains suggests 3D pentacene growth at parylene layer with small voids between grains and more than one monolayer step growth. The results will be utilized for optimization of the deposition process.