Abstract
In this paper, we propose an effective VLSI architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV (1 920×1 088) 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.
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Project (No. 20051321B01) supported by the Science and Technology Development Project of Hangzhou, China
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Li, Wy., Yu, L. Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder. J. Zhejiang Univ. Sci. A 9, 1638–1643 (2008). https://doi.org/10.1631/jzus.A0820112
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DOI: https://doi.org/10.1631/jzus.A0820112