Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

Abstract

This paper proposes a kind of programmable logic element (PLE) based on Sense-Switch pFLASH technology. By programming Sense-Switch pFLASH, all three-bit look-up table (LUT3) functions, partial four-bit look-up table (LUT4) functions, latch functions, and d flip flop (DFF) with enable and reset functions can be realized. Because PLE uses a choice of operational logic (COOL) approach for the operation of logic functions, it allows any logic circuit to be implemented at any ratio of combinatorial logic to register. This intrinsic property makes it close to the basic application specific integrated circuit (ASIC) cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring Sense-Switch pFLASH and PLE circuits, the results show that the “on” state driving current of the Sense-Switch pFLASH is about 245.52 µA, and that the “off” state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 ns, and the delay of the sequential logic operation DFF is 0.65 ns, both of which meet the requirements of the design technical index.

摘要

本文提出一种基于 Sense-Switch 型 pFLASH 技术的可编程逻辑单元(PLE)。通过对 Sense-Switch 型 pFLASH 进行编程, 实现所有的三位查找表 (LUT3) 功能、部分 LUT4 功能、锁存器功能以及带使能和复位的 DFF 功能。因为 PLE 使用了一种选择运算逻辑 (COOL) 的方法来运算逻辑函数, 它允许使用任意组合逻辑和寄存器的比例来实现任意逻辑电路。这一本质特性使其在精细粒度方面接近于基本的 ASIC 单元, 从而允许类似 ASIC 的基于单元的映射器应用其所有的优化潜力。对 Sense-Switch 型 FLASH 和 PLE 电路的实测结果表明 Sense-Switch 型 pFLASH 的 “开态” 驱动电流约为245.52 µA、 “关态” 漏电流约为0.1 pA; PLE 的可编程功能正常工作; 典型的组合逻辑运算 AND3 的延迟为 0.69 ns、时序逻辑 DFF 的延迟为 0.65 ns, 均满足设计技术指标的要求。