Reversible binary subtractor design using quantum dot-cellular automata

Article
  • 49 Downloads

Abstract

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.

Key words

Quantum dot-cellular automata (QCA) Reversible logic DG gate Binary subtractor Quantum cost 

CLC number

TN91 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Abdullah-Al-Shafi, M., 2016. Synthesis of Peres and R logic circuits in nanoscopic scale. Commun. Appl. Electron., 4(1):20–25. https://doi.org/10.5120/cae2016652004CrossRefGoogle Scholar
  2. Akter, R., Islam, N., Waheed, S., 2015. Implementation of reversible logic gate in quantum dot cellular automata. Int. J. Comput. Appl., 109(1):41–44. https://doi.org/10.5120/19155-0591Google Scholar
  3. Arjmand, M.M., Soryani, M., Navi, K., 2013. Coplanar wire crossing in quantum cellular automata using a ternary cell. IET Circ. Dev. Syst., 7(5):263–272. https://doi.org/10.1049/iet-cds.2012.0366CrossRefGoogle Scholar
  4. Bahar, A.N., Waheed, S., Hossain, N., 2015. A new approach of presenting reversible logic gate in nanoscale. Springer-Plus, 4:153. https://doi.org/10.1186/s40064-015-0928-4CrossRefGoogle Scholar
  5. Das, J.C., De, D., 2012. Quantum dot-cellular automata based cipher text design for nano-communication. Proc. Int. Conf. on Radar, Communication and Computing, p.224–229. https://doi.org/10.1109/ICRCC.2012.6450583Google Scholar
  6. Das, J.C., De, D., 2015. Reversible binary to grey and grey to binary code converter using QCA. IETE J. Res., 61(3): 223–229. https://doi.org/10.1080/03772063.2015.1018845CrossRefGoogle Scholar
  7. Das, J.C., De, D., 2016a. Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication. Front. Inform. Technol. Electron. Eng., 17(3):224–236. https://doi.org/10.1631/FITEE.1500079Google Scholar
  8. Das, J.C., De, D., 2016b. User authentication based on quantum-dot cellular automata using reversible logic for secure nanocommunication. Arab. J. Sci. Eng., 41(3):773–784. https://doi.org/10.1007/s13369-015-1870-zMathSciNetCrossRefGoogle Scholar
  9. Das, J.C., De, D., 2016c. Optimized design of reversible gates in quantum dot-cellular automata: a review. Rev. Theor. Sci., 4(3):279–286. https://doi.org/10.1166/rits.2016.1062CrossRefGoogle Scholar
  10. Das, J.C., De, D., 2016d. Novel low power reversible encoder design using quantum-dot cellular automata. J. Nanoelectron. Optoelectron., 11(4):450–458. https://doi.org/10.1166/jno.2016.1932CrossRefGoogle Scholar
  11. Das, J.C., De, D., 2016e. Novel low power reversible binary incrementer design using quantum-dot cellular automata. Microproc. Microsyst., 42:10–23. https://doi.org/10.1016/j.micpro.2015.12.004CrossRefGoogle Scholar
  12. Das, J.C., De, D., 2016f. Reversible comparator design using quantum dot-cellular automata. IETE J. Res., 62(3):323–330. https://doi.org/10.1080/03772063.2015.1088407CrossRefGoogle Scholar
  13. Das, J.C., Debnath, B., De, D., 2015. Image steganography using quantum dot-cellular automata. Quant. Matter, 4(5):504–517. https://doi.org/10.1166/qm.2015.1225CrossRefGoogle Scholar
  14. Das, K., De, D., 2010a. Novel approach to design a testable conservative logic gate for QCA implementation. IEEE 2nd Int. Advance Computing Conf., p.82–87. https://doi.org/10.1109/IADCC.2010.5423034Google Scholar
  15. Das, K., De, D., 2010b. Characterization, test and logic synthesis of novel conservative and reversible logic gates for QCA. Int. J. Nanosci., 9(3):201–214. https://doi.org/10.1142/S0219581X10006594CrossRefGoogle Scholar
  16. Das, K., De, D., 2011. Characterisation, applicability and defect analysis for tiles nanostructure of quantum dot cellular automata. Mol. Simul., 37(3):210–225. https://doi.org/10.1080/08927022.2010.536543CrossRefGoogle Scholar
  17. Das, K., De, D., De, M., 2013. Realisation of semiconductor ternary quantum dot cellular automata. IET Micro Nano Lett., 8(5):258–263. https://doi.org/10.1049/mnl.2012.0618CrossRefGoogle Scholar
  18. Debnath, B, Das, J.C., De, D., 2017. Reversible logic-based image steganography using quantum dot cellular automata for secure nanocommunication. IET Circ. Dev. Syst., 11(1):58–67. https://doi.org/10.1049/iet-cds.2015.0245CrossRefGoogle Scholar
  19. Dehghan, B., Roozbeh, A., Zare, J., 2014. Design of low power comparator using DG gate. Circ. Syst., 5(1):7–12. https://doi.org/10.4236/cs.2014.51002CrossRefGoogle Scholar
  20. Dey, A., Das, K., De, D., et al., 2012. Probabilistic defect analysis model for quantum dot cellular automata design at analytical phase. Int. J. Comput. Appl., 55(7):33–41. https://doi.org/10.5120/8768-2693Google Scholar
  21. Farazkish, R., Khodaparast, F., 2015. Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata. Microprocess. Microsyst., 39(6):426–433. https://doi.org/10.1016/j.micpro.2015.04.004CrossRefGoogle Scholar
  22. Ghosh, B., Agarwal, A., Akram, M.W., 2014a. An efficient quantum-dot cellular automata multi-bit adder design using 5-input majority gate. Quant. Matter, 3(5):448–453. https://doi.org/10.1166/qm.2014.1145CrossRefGoogle Scholar
  23. Ghosh, B., Giridhar, M., Nagaraju, M., et al., 2014b. Ripple carry adder using five input majority gates in quantum dot cellular automata. Quant. Matter, 3(6):495–498. https://doi.org/10.1166/qm.2014.1152CrossRefGoogle Scholar
  24. Gladshtein, M., 2013. Design and simulation of novel adder/subtractors on quantum-dot cellular automata: radical departure from Boolean logic circuits. Microelectron. J., 44(6):545–552. https://doi.org/10.1016/j.mejo.2013.03.013CrossRefGoogle Scholar
  25. Hashemi, S., Navi, K., 2014. Reversible multiplexer design in quantum-dot cellular automata. Quant. Matter, 3(6):523–528. https://doi.org/10.1166/qm.2014.1158CrossRefGoogle Scholar
  26. Hayati, M., Rezaei, A., 2014. New approaches for modeling and simulation of quantum-dot cellular automata. J. Comput. Electron., 13(2):537–546. https://doi.org/10.1007/s10825-014-0565-0CrossRefGoogle Scholar
  27. Hennessy, K., Lent, C.S., 2001. Clocking of molecular quantum- dot cellular automata. J. Vac. Sci. Technol. B, 19(5):1752–1755. https://doi.org/10.1116/1.1394729CrossRefGoogle Scholar
  28. Hung, W.N.N., Song, X.Y., Yang, G.W., et al., 2006. Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 25(9): 1652–1663. https://doi.org/10.1109/TCAD.2005.858352CrossRefGoogle Scholar
  29. ITRS, 2005. International Technology Roadmap for Semiconductors. http://www.itrs.netGoogle Scholar
  30. Janez, M., Pecar, P., Mraz, M., 2012. Layout design of manufacturable quantum-dot cellular automata. Microelectron. J., 43(7):501–513. https://doi.org/10.1016/j.mejo.2012.03.007CrossRefGoogle Scholar
  31. Karim, F., Walus, K., 2014. Calculating the steady-state polarizations of quantum cellular automata (QCA) circuits. J. Comput. Electron., 13(3):569–584. https://doi.org/10.1007/s10825-014-0573-0CrossRefGoogle Scholar
  32. Kianpour, M., Sabbaghi-Nadooshan, R., 2014. A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata. Microprocess. Microsyst., 38(8):1046–1062. https://doi.org/10.1016/j.micpro.2014.08.001CrossRefMATHGoogle Scholar
  33. Lakshmi, S.K., Rajakumar, G., Saminathan, A.G., 2015. Design and analysis of sequential circuits using nanotechnology based quantum dot cellular automata. J. Nanoelectron. Optoelectron., 10(5):601–610. https://doi.org/10.1166/jno.2015.1813CrossRefGoogle Scholar
  34. Landauer, R., 1961. Irreversibility and heat generation in the computing process. IBM J. Res. Dev., 5(3):183–191. https://doi.org/10.1147/rd.53.0183MathSciNetCrossRefMATHGoogle Scholar
  35. Lent, C.S., Tougaw, P.D., 1997. A device architecture for computing with quantum dots. Proc. IEEE, 85(4):541–557. https://doi.org/10.1109/5.573740CrossRefGoogle Scholar
  36. Lent, C.S., Tougaw, P.D., Porod, W., et al., 1993. Quantum cellular automata. Nanotechnology, 4(1):49–57. https://doi.org/10.1088/0957-4484/4/1/004CrossRefGoogle Scholar
  37. Ma, X.J., Huang, J., Metra, C., et al., 2009. Detecting multiple faults in one-dimensional arrays of reversible QCA gates. J. Electron. Test., 25(1):39–54. https://doi.org/10.1007/s10836-008-5078-yCrossRefGoogle Scholar
  38. Mano, M.M., Ciletti, M.D., 2011. Digital Design: with an Introduction to the Verilog HDL. Prentice Hall, India.Google Scholar
  39. Orlov, A.O., Amlani, I., Bernstein, G.H., et al., 1997. Realization of a functional cell for quantum-dot cellular automata. Science, 277(5328):928–930. https://doi.org/10.1126/science.277.5328.928CrossRefGoogle Scholar
  40. Ottavi, M., Pontarelli, S., DeBenedictis, E.P., et al., 2011. Partially reversible pipelined QCA circuits: combining low power with high throughput. IEEE Trans. Nanotechnol., 10(6):1383–1393. https://doi.org/10.1109/TNANO.2011.2147796CrossRefGoogle Scholar
  41. Pradhan, N., De, D., 2013. Spin transfer torque driven magnetic QCA cells. In: Giri, P., Goswami, D., Perumal, A. (Eds.), Advanced Nanomaterials and Nanotechnology. Springer Berlin Heidelberg, p.561–569. https://doi.org/10.1007/978-3-642-34216-5_56Google Scholar
  42. Saravanan, P., Kalpana, P., 2013. A novel and systematic approach to implement reversible gates in quantum dot cellular automata. WSEAS Trans. Circ. Syst., 12(10):307–316.Google Scholar
  43. Sen, B., Dutta, M., Sikdar, B.K., 2014. Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing. Microelectron. J., 45(2):239–248. https://doi.org/10.1016/j.mejo.2013.11.008CrossRefGoogle Scholar
  44. Shah, N.A., Khanday, F.A., Iqbal, J., 2012. Quantum-dot cellular automata (QCA) design of multi-function reversible logic gate. Commun. Inform. Sci. Manag. Eng., 2(4):8–18.Google Scholar
  45. Smolin, J.A., DiVincenzo, D.P., 1996. Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Phys. Rev. A, 53(4):2855–2856. https://doi.org/10.1103/PhysRevA.53.2855CrossRefGoogle Scholar
  46. Thapliyal, H., Ranganathan, N., 2009a. Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits. Proc. 22nd Int. Conf. on VLSI Design, p.511–516. https://doi.org/10.1109/VLSI.Design.2009.75Google Scholar
  47. Thapliyal, H., Ranganathan, N., 2009b. Design of efficient reversible binary subtractors based on a new reversible gate. IEEE Computer Society Annual Symp. on VLSI, p.229–234. https://doi.org/10.1109/ISVLSI.2009.49Google Scholar
  48. Thapliyal, H., Ranganathan, N., 2010. Reversible logic-based concurrently testable latches for molecular QCA. IEEE Trans. Nanotechnol., 9(1):62–69. https://doi.org/10.1109/TNANO.2009.2025038CrossRefGoogle Scholar
  49. Thapliyal, H., Srinivas, M.B., Arabnia, H., 2005. Reversible logic synthesis of half, full and parallel subtractors. Proc. Int. Conf. on Embedded Systems and Applications, p.165–181.Google Scholar
  50. Thapliyal, H., Ranganathan, N., Kotiyal, S., 2013. Design of testable reversible sequential circuits. IEEE Trans. VLSI Syst., 21(7):1201–1209. https://doi.org/10.1109/TVLSI.2012.2209688CrossRefGoogle Scholar
  51. Vankamamidi, V., Ottavi, M., Lombardi, F., 2005. A linebased parallel memory for QCA implementation. IEEE Trans. Nanotechnol., 4(6):690–698. https://doi.org/10.1109/TNANO.2005.858589CrossRefGoogle Scholar
  52. Yang, X.K., Cai, L., Kang, Q., et al., 2012. Clocking misalignment tolerance of pipelined magnetic QCA architectures. Microelectron. J., 43(6):386–392. https://doi.org/10.1016/j.mejo.2012.02.005CrossRefGoogle Scholar
  53. Zhang, R.M., Walus, K., Wang, W., et al., 2004. A method of majority logic reduction for quantum cellular automata. IEEE Trans. Nanotechnol., 3(4):443–450. https://doi.org/10.1109/TNANO.2004.834177CrossRefGoogle Scholar

Copyright information

© Zhejiang University and Springer-Verlag GmbH Germany, part of Springer Nature 2017

Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringWest Bengal University of TechnologyKolkataIndia
  2. 2.Department of PhysicsUniversity of Western AustraliaWAAustralia

Personalised recommendations