Design and analysis of carbon nanotube FET based quaternary full adders

  • Mohammad Hossein Moaiyeri
  • Shima Sedighiani
  • Fazel Sharifi
  • Keivan Navi


CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.


Nanoelectronics Carbon nanotube FET Multiple-valued logic Quaternary logic 

CLC number



  1. Asif, S., Vesterbacka, M., 2012. Performance analysis of radix-4 adders. Integr. VLSI J., 45(2): 111–120. Scholar
  2. Balamurugan, G., Shanbhag, N.R., 2001. The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Sol.-State Circ., 36(2): 273–280. Scholar
  3. Chen, Y., Wang, B., Poa, P.C.H., et al., 2007. (n, m) selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts. J. Am. Chem. Soc., 129(29): 9014–9019. Scholar
  4. da Silva, R.C.G., Boudinov, H.I., Carro, L., 2006. A low power high performance CMOS voltage-mode quaternary full adder. IFIP Int. Conf. on Very Large Scale Integration, p.1130–1133. Scholar
  5. Datla, R., 2009. Design and Validation of Quaternary Arithmetic Circuits. PhD Thesis, Southern Methodist University, USA.Google Scholar
  6. Datla, S.R., Thornton, M.A., Hendrix, L., et al., 2009. Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with System Verilog©. 39th IEEE Int. Symp. on Multiple-Valued Logic, p.256–261. Scholar
  7. Deng, J., 2007. Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors. PhD Thesis, Stanford University, USA.Google Scholar
  8. Deng, J., Wong, H.S.P., 2007a. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. Electron Dev., 54(12): 3186–3194. Scholar
  9. Deng, J., Wong, H.S.P., 2007b. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Dev., 54(12): 3195–3205. Scholar
  10. Dubrova, E., 1999. Multiple-valued logic in VLSI: challenges and opportunities. Proc. NORCHIP Conf., p.340–350.Google Scholar
  11. Gelao, G., Marani, R., Diana, R., et al., 2011. Semi-empirical SPICE model for n-type conventional CNTFETs. IEEE Trans. Nanotechnol., 10(3): 506–512. Scholar
  12. Hurst, S.L., 1984. Multiple-valued logic—its status and its future. IEEE Trans. Comput., 33(12): 1160–1179. Scholar
  13. Kim, Y.B., Kim, Y.B., Lombardi, F., 2009. Novel design methodology to optimize the speed and power of the CNTFET circuits. 52nd IEEE Int. Midwest Symp. on Circuits and Systems, p.1130–1133. Scholar
  14. Liang, J., Chen, L., Han, J., et al., 2014. Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Trans. Nanotechnol., 13(4): 695–708. Scholar
  15. Lin, A., Patil, N., Ryu, K., et al., 2009. Threshold voltage and on–off ratio tuning for multiple-tube carbon nanotube FETs. IEEE Trans. Nanotechnol., 8(1): 4–9. Scholar
  16. Lin, S., Kim, Y.B., Lombardi, F., 2011. CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol., 10(2): 217–225. Scholar
  17. Mansoori, G.A., Soelaiman, T.F., 2005. Nanotechnology—an introduction for the standards. J. ASTM Int., 2(6): 1–21. Scholar
  18. Marani, R., Perri, A.G., 2011. A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software. Current Nanosci., 7(2): 245–253. Scholar
  19. Marani, R., Perri, A.G., 2012. A DC model of carbon nanotube field effect transistor for CAD applications. Int. J. Electron., 99(3): 427–444. Scholar
  20. Marani, R., Perri, A.G., 2014. Modelling of CNTFETs for computer aided design of A/D electronic circuits. Current Nanosci., 10(3): 326–333. Scholar
  21. Marani, R., Gelao, G., Perri, A.G., 2013. Modelling of carbon nanotube field effect transistors oriented to SPICE software for A/D circuit design. Microelectron. J., 44(1): 33–39. Scholar
  22. Marani, R., Gelao, G., Perri, A.G., 2014. Comparison of ABM SPICE library with Verilog-A for compact CNTFET model implementation. Current Nanosci., 8(4): 556–565. Scholar
  23. Moaiyeri, M.H., Doostaregan, A., Navi, K., 2011. Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circ. Dev. Syst., 5(4): 285–296. Scholar
  24. Moaiyeri, M.H., Navi, K., Hashemipour, O., 2012. Design and evaluation of CNFET-based quaternary circuits. Circ. Syst. Signal Process., 31(5): 1631–1652. Scholar
  25. Navi, K., Doostaregan, A., Moaiyeri, M.H., et al., 2011. A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. Fuzzy Sets Syst., 185(1): 111–124. Scholar
  26. Patel, V., Gurumurthy, K.S., 2010. Arithmetic operations in multi-valued logic. Int. J. VLSI Des. Commun. Syst., 1(1): 21–32.CrossRefGoogle Scholar
  27. Pedram, M., Wu, X., 1997. A new description of MOS circuits at switch-level with applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 80(10): 1892–1901.Google Scholar
  28. Raychowdhury, A., Roy, K., 2005. Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol., 4(2): 168–179. Scholar
  29. Raychowdhury, A., Roy, K., 2007. Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circ. Systems I, 54(11): 2391–2401. Scholar
  30. Sharifi, F., Moaiyeri, M.H., Navi, K., et al., 2015. Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron., 14(3): 762–772. Scholar
  31. Thoidis, I., Soudris, D., Karafyllidis, I., et al., 1998. Quaternary voltage-mode CMOS circuits for multiple-valued logic. IEE Proc.-Circ. Dev. Syst., 145(2): 71–77. Scholar
  32. Wu, X., 1992. Theory of transmission switches and its application to design of CMOS digital circuits. Int. J. Circ. Theory Appl., 20(4): 349–356. Scholar
  33. Wu, X., Prosser, F., 1996. Design theory of digital circuits at switch level. Sci. China Technol. Sci., 39(4): 424–434.MATHGoogle Scholar
  34. Yang, F., Wang, X., Zhang, D., et al., 2014. Chirality-specific growth of single-walled carbon nanotubes on solid alloy catalysts. Nature, 510(7506): 522–524. Scholar

Copyright information

© Journal of Zhejiang University Science Editorial Office and Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Mohammad Hossein Moaiyeri
    • 1
    • 2
  • Shima Sedighiani
    • 2
  • Fazel Sharifi
    • 2
  • Keivan Navi
    • 2
  1. 1.Faculty of Electrical EngineeringShahid Beheshti UniversityTehranIran
  2. 2.Nanotechnology and Quantum Computing LabShahid Beheshti UniversityTehranIran

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