In 1982, the Semiconductor Industry Association formed the Semiconductor Research Corporation (SRC) to launch and manage relevant, collaborative university research and workforce development programs. The SRC “founding fathers” were Erich Bloch, a vice president of IBM, then Director of the National Science Foundation; Robert Noyce, co-founder of Intel and co-inventor of the integrated circuit; and Jack Kilby of Texas Instruments, Nobel Prize Laureate for the invention of the integrated circuit. During its first ten years, the SRC launched the International Technology Roadmap for Semiconductors (ITRS), which served as a Master Plan for the global semiconductor industry for two decades. The first all-industry strategic plan, ITRS is a big win of SRC’s early years. ITRS mostly focused on minimum feature size of transistors and 2-dimensional scaling and helped to understand many physical limits of scaling and performance, developing technologies to go as far as possible toward these limits.

Today, 40 years later, SRC realized two things: that Information/Data is the social-economic growth engine of civilization and that there are physical limits driven by sustainability. In recognition of these facts, SRC has brought forward the new Microelectronics and Advanced Packaging (MAPT) Roadmap [1] which brings attention to expanding our advanced chip-making and chip-packaging efforts into three dimensions as one of the research priorities that can help us meet the needs of future generations. The MAPT Roadmap is built on the Decadal Plan for Semiconductor [2], which talks about system-level goals. For the next microelectronic system revolution, emerging materials and physics will be leveraged for new advanced packaging solutions that can have system-level benefits.

This special issue of MRS Advances called for recent research advances in the area of new microelectronic materials and devices. The topics of these articles include low melting temperature Sn–Bi alloys for lead-free solders in electronics packaging [3], development of 300–400 °C grown diamond for semiconductor devices thermal management [4], Circuits and magnetics co-design for ultra-thin vertical power electronics [5].