Abstract
The drive toward higher density and higher performance in integrated circuits creates a need to keep interconnects short and eliminate layers of packaging. In this article, we propose a novel, ultrahigh-density (exceeding 104 leads per cm2), compliant, wafer-level, input/output interconnection technology called “sea of leads” as a key enabling technology for future high-performance microsystems. The mechanical compliance is addressed through slippery leads (leads released from the surface) and embedded air gaps. The ability to fabricate embedded air gaps has enabled the integration of optical interconnects with high index-of-refraction mismatches between the core and cladding.
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J.D. Meindl, J.A. Davis, Zarkesh-P. Ha, C.S. Patel, K.P. Martin, and P.A. Kohl, IBM J. Res. Dev. 46 (2002) p. 245.
J.D. Meindl, R. Venkatesan, J.A. Davis, J. Joyner, A. Naeemi, Zarkesh-P. Ha, M.S. Bakir, Mulé A.V., P.A. Kohl, and K.P. Martin, in IEEE Int. Electron Devices Meet. Tech. Dig. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2001) p. 525.
2001 International Technology Roadmap for Semiconductors (ITRS) (Semiconductor Industry Association, San Jose, 2001).
M.S. Bakir, H.A. Reed, P.A. Kohl, K.P. Martin, and J.D. Meindl, in Proc. IEEE Electronic Components and Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2002) p. 1087.
M.S. Bakir, H.A. Reed, Mulé A.V., P.A. Kohl, K.P. Martin, and J.D. Meindl, in Proc. Custom Integrated Circuits Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2002) p. 491.
C.S. Patel, “Compliant Wafer-Level Package (CWLP),” PhD dissertation, Georgia Institute of Technology, 2001.
C.S. Patel, C. Power, M. Realff, P.A. Kohl, K.P. Martin, and J.D. Meindl, in Proc. Int. Conf. on High-Density Interconnect and Systems Packaging (International Microelectronics and Packaging Society, Washington, DC, and CMP Media, Manhasset, NY, 2000) p. 335.
H.D. Thacker, M.S. Bakir, D. Keezer, K.P. Martin, and J.D. Meindl, in Proc. IEEE Electronic Components and Technology Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2002) p. 1188.
H.A. Reed, C.E. White, V. Rao, S.A. Allen, C.L. Henderson, and P.A. Kohl, J. Micromech. Microeng. 11 (2001) p. 733.
X. Wu, H.A. Reed, L.F. Rhodes, E. Elce, R. Ravikiran, R.A. Shick, C.L. Henderson, Bidstrup S.A. Allen, and P.A. Kohl, J. Electrochem. Soc. 149 (10) (2002) p. S79.
X. Wu, H.A. Reed, L.F. Rhodes, E. Elce, R. Ravikiran, R.A. Shick, C.L. Henderson, S.A. Allen, and P.A. Kohl, J. Appl. Polym. Sci. in press.
S.M. Schultz, E.N. Glytsis, and T.K. Gaylord, Opt. Lett. 24 (1999) p. 1708.
M. Jones, PhD thesis, Georgia Institute of Technology, 1995.
R. Villalaz, E.N. Glytsis, and T.K. Gaylord, Appl. Opt. 41 (2002) p. 5223.
A.V. Mulé, M. Bakir, J.P. Jayachandran, R. Villalaz, H. Reed, K. Martin, P. Kohl, E. Glytsis, T. Gaylord, J. Meindl, N. Agrawal, S. Ponoth, J. Plawsky, and P. Persans, in Proc. IEEE Int. Interconnect Tech. Conf. (Institute of Electrical and Electronics Engineers, Piscataway, NJ, 2002) p. 122.
A. Jain, S. Rogojevic, S. Ponoth, N. Agarwal, I. Matthew, W.N. Gill, P. Persans, M. Tomozawa, J.L. Plawsky, and E. Simonyi, Thin Solid Films 513 (2001) p. 398.od]20110131
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Bakir, M.S., Reed, H.A., Mulé, A.V. et al. Chip-to-Module Interconnections Using “Sea of Leads” Technology. MRS Bulletin 28, 61–67 (2003). https://doi.org/10.1557/mrs2003.19
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DOI: https://doi.org/10.1557/mrs2003.19