Abstract
In this article, we have explored the interface states that form between the channel of a monolayer MoS2 transistor and a high-κ gate dielectric. These interface states lead to large hysteresis in the drain current versus gate voltage characteristic or the so-called transfer characteristic of the transistor. By applying carefully designed pulses to the gate of the transistor, we show that it is possible to both understand the nature of the interface states and minimize the hysteresis, so that the transfer characteristic can be reliably used for subsequent extraction of material parameters such as mobility.
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ACKNOWLEDGMENTS
This work was supported in part by the AFOSR YIP #FA9550-13-l-0114, the ARO YIP # W911 NF‐13‐1‐0224 and the NSF CAREER Award No. CCF‐1149804.
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Lu, Z., Lee, O., Wong, J.C. et al. Surface states in a monolayer MoS2 transistor. Journal of Materials Research 31, 911–916 (2016). https://doi.org/10.1557/jmr.2015.405
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DOI: https://doi.org/10.1557/jmr.2015.405