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On-chip tensile testing of nanoscale silicon free-standing beams

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Abstract

Nanomechanical testing of silicon is primarily motivated toward characterizing scale effects on the mechanical behavior. “Defect-free” nanoscale silicon additionally offers a road to large deformation permitting the investigation of transport characteristics and surface instabilities of a significantly perturbed atomic arrangement. The need for developing simple and generic characterization tools to deform free-standing silicon beams down to the nanometer scale, sufficiently equipped to investigate both the mechanical properties and the carrier transport under large strains, has been met in this research through the design of a versatile lab-on-chip. The original on-chip characterization technique has been applied to monocrystalline Si beams produced from Silicon-on-Insulator wafers. The Young’s modulus was observed to decrease from 160 GPa down to 108 GPa when varying the thickness from 200 down to 50 nm. The fracture strain increases when decreasing the volume of the test specimen to reach 5% in the smallest samples. Additionally, atomic force microscope-based characterizations reveal that the surface roughness decreases by a factor of 5 when deforming by 2% the Si specimen. Proof of concept transport measurements were also performed under deformation up till 3.5% on 40-nm-thick lightly p-doped silicon beams.

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Acknowledgments

The authors express gratitude for access to MC2, Nano-fabrication Laboratory, Chalmers University of Technology, Department of Microtechnology and Nanoscience, Sweden, and Prof. Ulf Södervall for the fruitful discussions. The authors would especially like to thank the European Network of Excellence (FP7) NANOSIL and MINATIS consortia for funding this research.

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Authors and Affiliations

  1. Research Center in Micro and Nanoscopic Materials and Electronic Devices, Université Catholique de Louvain, B-1348, Louvain-la-Neuve, Belgium

    Umesh Bhaskar, Vikram Passi & Samer Houri

  2. Institute of Information and Communication Technologies, Electronics and Applied Mathematics, Université Catholique de Louvain, B-1348, Louvain-la-Neuve, Belgium

    Enrique Escobedo-Cousin & Sarah H. Olsen

  3. Newcastle University, School of Electrical, Electronic & Computer Engineering, NE1 7RU, Newcastle upon Tyne, United Kingdom

    Thomas Pardoen

  4. Institute of Mechanics, Materials and Civil Engineering, Université Catholique de Louvain, B-1348 Louvain-la-Neuve, Belgium

    Jean-Pierre Raskin

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  1. Umesh Bhaskar
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Correspondence to Umesh Bhaskar.

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Bhaskar, U., Passi, V., Houri, S. et al. On-chip tensile testing of nanoscale silicon free-standing beams. Journal of Materials Research 27, 571–579 (2012). https://doi.org/10.1557/jmr.2011.340

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