Abstract
As the scaling of the device dimensions in CMOS devices runs into physical limitations, new materials beyond Si with high electron and hole mobilities such as Ge, SiGe, and III-V materials are introduced. Challenges of CMP for these materials are reviewed in this paper. First we discussed the challenge of the new integration schemes to CMP. Loading effects can result in different growth rates for varying feature sizes, which results in a critical dimension dependent overburden. This makes it more difficult to meet the targets of the CMP process with respect to oxide loss and Ge/SiGe/III-V dishing. Secondly we discuss the challenge for the reduction of the defects during CMP for these new materials. Finally the challenge that is relevant especially for the introduction of III-V materials is studied. During the polishing of III-V materials, toxic gases as well as III-V containing liquid waste will be created. The chemical mechanism of the waste control is discussed.
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Zhang, J.H., Tsai, S., Surisetty, C. et al. CMP Challenges for Advanced Technology Nodes beyond Si. MRS Advances 2, 2891–2902 (2017). https://doi.org/10.1557/adv.2017.339
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DOI: https://doi.org/10.1557/adv.2017.339