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Impact of printed wiring board coatings on the reliability of lead-free chip-scale package interconnections

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Abstract

When lead-free solder alloys mix with lead-free component and board metallizations during reflow soldering, the solder interconnections become multicomponent alloy systems whose microstructures cannot be predicted on the basis of the SnPb metallurgy. To better understand the influences of these microstructures on the reliability of lead-free electronics assemblies, SnAgCu-bumped components were reflow-soldered with near-eutectic SnAgCu solder pastes on Ni(P)|Au- and organic solderability preservative (OSP)-coated printed wiring boards and tested under cyclic thermal shock loading conditions. The reliability performance under thermomechanical loading was found to be controlled by the kinetics of recrystallization. Because ductile fracturing of the as-soldered tin-rich colonies would require a great amount of plastic work, the formation of continuous network of grain boundaries by recrystallization is needed for cracks to nucleate and propagate intergranularly through the solder interconnections. Detailed microstructural observations revealed that cracks nucleate and grow along the grain boundaries especially between the recrystallized part and the non-recrystallized part of the interconnections. The thermal cycling test data were analyzed statistically by combining the Weibull statistics and the analysis of variance. The interconnections on Ni(P)|Au were found out to be more reliable than those on Cu|OSP. This is due to the extensive dissolution of Cu conductor, in the case of the Cu|OSP assemblies, into molten solder that makes the microstructure to differ noticeably from that of the Ni(P)|Au interconnections. Because of large primary Cu6Sn5 particles, the Cu-enriched interconnections enhance the onset of recrystallization, and cracking of the interconnections is therefore faster. The solder paste composition had no statistically significant effect on the reliability performance.

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Mattila, T.T., Vuorinen, V. & Kivilahti, J.K. Impact of printed wiring board coatings on the reliability of lead-free chip-scale package interconnections. Journal of Materials Research 19, 3214–3223 (2004). https://doi.org/10.1557/JMR.2004.0436

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