Skip to main content
SpringerLink
Log in

Full-IC manufacturability check based on dense silicon imaging

  • Published:
Science in China Series F: Information Sciences Aims and scope Submit manuscript

Abstract

With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ∼16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Ogawa, K., Ashida, I., Kawahira, H., New mask data verification method after optical proximity effect correction, SPIE, 2001, 4409: 186–193.

    Article  Google Scholar 

  2. Malhotra, V., Chang, F., Verifying the ‘correctness’ of your optical proximity correction designs, SPIE, 1999, 3679: 130–137.

    Article  Google Scholar 

  3. Wong, A. K., Microlithography: Trends, challenges, solutions, and their impact on design, Micro, IEEE, 2003, 23(2): 12–21.

    Article  Google Scholar 

  4. Karklin, L., Mazor, S., Joshi, D., Subwavelength lithography: An impact of photo mask errors on circuit performance, SPIE, 2002, 4691: 259–267.

    Article  Google Scholar 

  5. Yan, X., Chen, Y., Shi, Z., Architecture of a post-OPC silicon verification tool, Proc. ASICON, Beijing, China, 2003, 1365–1368.

  6. Kahng, A. B., Pati, Y., Subwavelength lithography and its potential impact on design and EDA, Proc. ACM/IEEE Design Automation Conf., New Orlears, LA, USA, 1999, 799–804.

  7. Rieger, M., Mayhew, J., Panchapakesan, S., Layout design methodology for sub-wavelength manufacturing, Proc. ACM/IEEE Design Automation Conf., Las Vegas, NV, USA, 2001, 85–88.

  8. Stirniman, J., Rieger, M., Spatial-filter models to describe IC lithographic behavior, SPIE, 1997, 3051: 469–478.

    Article  Google Scholar 

  9. Chen, Z., Shi, Z., Wang, G. et al., A new method of 2D contour extraction for fast simulation of photolithographic process, Chinese Journal of Semiconductors, 2002, 23(7): 766–771.

    Google Scholar 

  10. Granik, Y., Cobb, N., Do, T., Universal process modeling with VTRE for OPC, SPIE, 2002, 4691: 377–394.

    Article  Google Scholar 

  11. Pati, Y., Kailath, T., Phase-shifting masks for microlithography: Automated design and mask requirements, Journal of the Optical Society of America A-Optics Image Science and Vision, 1994, 11(9): 2438–2452.

    Article  Google Scholar 

  12. Cobb, N., Zakhor, A., A mathematical and CAD framework for proximity correction, SPIE, 1996, 2726: 208–222.

    Article  Google Scholar 

  13. Sahouria, E., Granik, Y., Cobb, N. et al., Full-chip process simulation for silicon DRC, International Conference on Modeling and Simulation of Microsystems, San Diego CA, USA, 2000, 33–35.

  14. Lee, S., Ka, C. N., Takachi, O. et al., LAVA web-based remote simulation: Enhancements for education and technology innovation, SPIE, 2001, 4346: 1500–1506.

    Article  Google Scholar 

  15. Cobb, N., Zakhor, A., Large-area phase-shift mask design, SPIE, 1994, 2197: 348–360.

    Article  Google Scholar 

  16. Qian, Q., Leon, F., Fast algorithms for 3D high NA lithography simulation, SPIE, 1995, 2440: 372–380.

    Article  Google Scholar 

  17. Bernard, D., Li, J., Rey, J., et al., Efficient computational techniques for aerial imaging simulation, SPIE, 1996, 2726: 273–287.

    Article  Google Scholar 

  18. Sorensen, H., Burrus, C., Efficient computation of the DFT with only a subset of input or output points, IEEE Transactions on Signal Processing, 1993, 41(3): 1184–1200.

    Article  MATH  Google Scholar 

  19. Dolainsky, C., Karakatsanis, P., Gans, F. et al., Simulation-based method for sidelobe suppression, SPIE, 2000, 4000: 1156–1162.

    Article  Google Scholar 

  20. Toublan, O., Cobb, N., Sahouria, E., Fully automatic side lobe detection and correction technique for attenuated phase-shift masks, SPIE, 2001, 4346: 1541–1547.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of VLSI Design, Zhejiang University, 310027, Hangzhou, China

    Yan Xiaolang, Shi Zheng, Chen Ye, Ma Yue & Gao Gensheng

Authors
  1. Yan Xiaolang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Shi Zheng
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chen Ye
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Ma Yue
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Gao Gensheng
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Chen Ye.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Yan, X., Shi, Z., Chen, Y. et al. Full-IC manufacturability check based on dense silicon imaging. Sci China Ser F 48, 533–544 (2005). https://doi.org/10.1360/04yf0115

Download citation

  • Received:

  • Issue Date:

  • DOI: https://doi.org/10.1360/04yf0115

Keywords

Search

Navigation