On the Baliga’s Figure-Of-Merits (BFOM) Enhancement of a Novel GaN Nano-Pillar Vertical Field Effect Transistor (FET) with 2DEG Channel and Patterned Substrate
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A novel enhancement-mode vertical GaN field effect transistor (FET) with 2DEG for reducing the on-state resistance (RON) and substrate pattern (SP) for enhancing the breakdown voltage (BV) is proposed in this work. By deliberately designing the width and height of the SP, the high concentrated electric field (E-field) under p-GaN cap could be separated without dramatically impacting the RON, turning out an enhanced Baliga’s Figure-Of-Merits (BFOM, BV2/RON). Verified by experimentally calibrated ATLAS simulation, the proposed device with a 700-nm-long and 4.6-μm-width SP features six times higher BFOM in comparison to the FET without patterned substrate. Furthermore, the proposed pillar device and the SP inside just occupy a nano-scale area, enabling a high-density integration of such devices, which renders its high potential in future power applications.
KeywordsGaN FET Nano-pillar Patterned substrate
Doping concentration of p-type GaN
Doping concentration of n-type GaN
Two-dimensional electron gas
Aluminum gallium nitride with a mole fraction of 0.23 for aluminum
Interface trap density of the substrate pattern
The difference between the conduction band and interface-trap energy-level
Field effect transistor
High electron mobility transistor
Height of the gate
Height of substrate pattern
Length of the device
Length of the Gate
Length of the p-GaN cap
Length of the substrate pattern
Vertical field effect transistor with substrate pattern
Depth of the device
Nowadays, wide bandgap semiconductors such as ZnO, In2O3, SiC, and gallium nitride (GaN) have attracted attention [1, 2, 3, 4, 5]. Whereas, considering the electronic properties, the lateral AlGaN/GaN high electron mobility transistor (HEMT) is widely considered as a potential candidate for substituting the Si-based device in power or frequency applications due to the higher breakdown voltage (BV) as well as the stronger thermal stability. A lot of efforts, such as p-type cap [6, 7], fluorine ion implantation [8, 9], thin barrier [10, 11], double channel [5, 12], and field-coupled gate , have been made on the realization of the enhancement-type HEMT that is desired to simplify the driver circuit.
These technologies face, however, many formidable challenges such as low uniformity of the threshold voltage, the waste of vertical chip area, current collapse, limited Baliga’s Figure-Of-Merits (BFOM), and so on. Especially, the contradiction between the drift length and the BV negatively influences the scaling-down of the device [14, 15]. In other words, smaller device leads to lower BV, in which it is harder to adopt the junction terminals that promote the BFOM by optimizing the electric field distribution. To this end, back barrier , buried junction , quantum well field plate , and other structures that are inserted into the lateral HEMT exhibiting the feature of the electrical field plate have been proposed to enhance BV by utilizing the vertical region of the chip.
On the other hand, by the virtue of the superior natures of GaN, the bulk GaN vertical field effect transistor (VFET) attracts more and more attention due to the easier realization of enhancement-type functionality and the full utilization of the vertical region [19, 20, 21, 22]. Many novel structures are presented by experiments or simulations to incline the BV and simultaneously reduce the on-state resistance (RON) [23, 24, 25]. However, not to mention the difficulties in fabricating the super-junction (SJ) in GaN, the lack of the high-mobility two-dimensional electron gas (2DEG) leads to a higher RON , which hinders the optimization of BFOM in such devices.
In this work, a novel enhancement-mode vertical GaN FET with 2DEG for reducing the RON and substrate pattern (SP) for enhancing the BV is proposed, wherein the combination of the 2DEG channel and the SP effectively balances the contradiction between the low on-state resistance and the high BV. Furthermore, the proposed device pillar and the SP inside just occupy a nano-scale area, enabling a high-density integration of such devices. Verified by numerical simulation constructed in ATLAS, the proposed device features higher BFOM compared with the same field effect transistor (FET) without the patterned substrate, rendering its high potential in future power applications.
The whole device therefore could be fabricated by a standard process successively: (1) the epitaxial deposition of the conduction substrate and the integrate SP layer, (2) the partial etching of the SP pattern, (3) the deposition and polishing of n-GaN buffer, (4) the deposition of AlGaN barrier and p-GaN cap, and (5) the fabrication of electrodes and passivation.
Value and unit
LD = 1 μm
WD = 1 μm
σp= 6.5 × 1012 cm−2
SP interface trap (Al2O3)
DSP = 8 × 1012 cm−2; ET = EC-0.5 eV
p-GaN cap length
LP = 0.4 to 0.7 μm
LW = 0 to 800 nm
HW = 0 to 4.7 μm
LG = 15 nm
LW = 0.17 μm
Result and Discussion
Figure 10b shows the calculated BFOM of the SP-VFET. Owing to the different increasing rate of BV and on-state resistance, the BFOM of all the devices firstly grow and then drop after the length of the SP longer than 400 nm. A peak BFOM of 125 MW/cm2 is achieved when the length reaches 700 nm and the height reaches 4.6 μm. Compared with the device without the SP, the proposed SP-VFET performs more than six times better in terms of the BFOM.
This improvement is achieved owning to the suppression of the high E-field under the p-GaN, thanks to the negatively charged interface trap around the SP. The interaction, which occurs between the trapped negative charge on the interface of the SP and the depletion region around the p-GaN, forms a new distribution of E-field mainly towards the trapped charge. According to the Gauss’ law, the electric flux is limited by the charge encircled. Thus, the introduced E-field will affect the electric flux toward elsewhere. As the negative charge of depletion region is the main source for the crowed E-field around p-GaN, the E-field introduced by the trapped charge will play a role in suppressing the E-field crowed around p-GaN, and consequently, BV is enhanced. Specifically, when the SP length is lower than 400 nm, the negative charge introduced by SP is far away from the depletion region. Thus, the E-field formed between the depletion region and trapped negative charge is too small to play a role in affecting the crowed E-field under p-GaN. And as a result, the BV of the device grows slightly. However, as the SP length is higher than 400 nm, owing to the more trapped negative charge on the interface of the SP and shorter distance between the depletion region and trapped negative charge, the E-field between the depletion region and trapped negative charge is enhanced, leading to the growth of the BV.
In this work, a novel enhancement-type GaN vertical FET (SP-VFET) with 2DEG channel and substrate pattern for improving the BFOM thereof is proposed and investigated. Verified by experimentally calibrated simulation implemented with ATLAS, it is the SP that relieves the E-field peak under the p-GaN, and simultaneously, attracts new E-field concentration across the SP that owns higher critical E-field. Consequently, the BV of the proposed SP-VFET is boosted with a moderately increasing on-state resistance due to the 2DEG compensation. The BFOM of the SP-VFET therefore is enhanced six times better than that of the device without the SP when the SP length and height are 700 nm and 4.6 μm respectively, rendering the promising potential of the proposed SP-VFET in high-density power integration.
All the authors are associated under the Undergraduate Training Program for Innovation and Entrepreneurship (No. 201810614067) with University of Electronic Science and Technology of China (UESTC).
This work was supported by Sichuan Science and Technology Program under Grant 2019YFH0006.
Availability of Data and Materials
The date generated during and/or analyzed during the current study are available from the corresponding authors on reasonable request.
ZW brought out the idea of the structure and supervised the simulation. ZW and ZZ carried out the simulations and analysis. DY created the figures and wrote the manuscript. YY supervised the whole work. All authors discussed the results and contributed to the final manuscript. All the authors have read and approved the final manuscript.
The authors declare that they have no competing interests.
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