# Performance analysis of multi-rate signal processing digital filters on FPGA

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## Abstract

Multi-rate signal processing, an important part of the design of a digital frequency converter, is realized mainly based on interpolation and decimation, which match the sampling rate between the baseband and high-frequency processing side, especially in down conversion. However, the design of a digital filter is important for realizing multi-rate interpolation and decimation, which is highlighted in this paper. To analyze the digital filter performance in multi-rate signal processing, the ordinary finite impulse response (FIR) filter and more efficient digital filter are discussed respectively. The ordinary FIR filters use a Hamming window to design, while a more efficient digital filter includes a cascaded integrate comb (CIC) and half-band filter. Sampling rate transformation factor is 12 in this design, which is cascaded by three stages. Each stage corresponding to the conversion factor is 3, 2, and 2. Both of these design methods are implemented on the FPGA development board. The hardware resource occupancy and the error rate of the signal amplitude in decimation show that the efficient digital filter is superior to the digital filter designed by the Hamming window in the real-time processing.

## Keywords

Multi-rate signal processing Decimation Hamming window FIR filter CIC Half-band filter FPGA## Abbreviations

- ADC
Analog to digital converter

- CIC
Cascaded integrate comb

- IF
Intermediate frequency

- NCO
Numerical control oscillator

## 1 Introduction

Multi-rate signal processing is the key technology to realize the digital frequency converter. In a general communication system, the rate of the baseband signal is often much lower than that of the intermediate frequency (IF) signal; in order to match the sampling rate of both sides, there is no doubt that the sampling rate of the former increases, which is equivalent to the increase in the number of sampling points. While in the reception process, signals from an analog to digital converter (ADC) with a higher rate are difficult to provide directly to processors for processing; as a result, extraction is considered to decrease the sampling rate. In other words, the discrete sampled signal is resampled, and ultimately, the signal frequency will be down to the appropriate point for data recovery. So interpolation and extraction is not only the basis of multi-rate signal processing, but also an important theoretical support for digital inverter design [1].

As the functional requirements of the system become more and more diversified, the function of the circuit module in the design becomes more and more complicated, and the higher processing speed of the chip is of great need. In other words, traditional analog circuits cannot meet the whole design demands. So those large-scale integrated devices, such as FPGA and DSP as high-speed signal processors, have been vigorously developed and promoted, which is characterized by the use of digital or software to replace the analog circuit [2]. At present, most of the transceivers include baseband signal processing, digital frequency conversion, and analog conversion. Analog frequency conversion aims at moving high-frequency analog signal to the appropriate IF, which can reduce the restrictions of key devices such as AD/DA, and digital frequency conversion is prone to get a lower rate baseband signal [3].

## 2 Methods

The simulations are based on FPGA Altera Develop Board. All the simulation results are calculated by ModelSim and Matlab2018.

## 3 Two designs of digital filter in multi-rate signal processing

Multi-rate signal processing is an important technique to be discussed. It consists of interpolation and decimation and also the corresponding design of digital filter before extraction or after interpolation. The composition of a digital frequency converter is similar to that of the analog frequency converter, mainly including the digital mixer, numerical control oscillator (NCO), and the low-pass filter. In comparison, analog frequency converter’s circuit functions are not stable enough and greatly affected by the temperature. However, a digital frequency converter not only can guarantee the orthogonality of IF carrier, but also conveniently modify the frequency interval and other parameters. Besides, the purpose of the sampling rate conversion is to match the rate of data processing, especially in receiver design; the frequency of the received IF signal after certain decimation will be reduced, thereby relieving the stress of subsequent data processing.

*x*(

*n*), the sampling rate is

*F*= 1/

*T*, and the input signal is full of the whole frequency, that is, −

*F*/2 ≤

*f*≤

*F*/2, the digital angular frequency

*ω*= 2

*πfT*. The output of sampling rate conversion is

*y*(

*n*), and the sampling rate changes to

*F*

^{'}= 1/

*T*

^{'}. The process of sampling rate conversion block diagram is shown in Fig. 2.

*D*and

*L*are positive integers, since it is a linear system, and the output sample sequence is also a linear combination of input samples, which can be expressed by Eq. (2):

when *D* = *L* = 1, it becomes a normal impulse response of the linear system in the case of constant sampling rate as we know.

*F*>

*F*

^{'}, the sampling rate gets lower, called decimation, according to the Fourier transform; it can be seen that the decimation of the signal in the time domain is equivalent to the broadening of the frequency domain. While

*F*<

*F*

^{'}, the sampling rate is rising up, called interpolation, which leads to the compression of the signal spectrum. Based on that theory, it can be known that the addition of the appropriate threshold filter before decimation or after interpolation can keep the spectral characteristic of the original signal. In addition, when the ratio in Eq. (1) is not a positive integer, then that is a fractional transform, which is achieved by

*L*-times interpolation first and then the

*D*-fold decimation; the structure is shown in Fig. 3, the

*L*-times interpolation is on the left of the block diagram and the

*D*-decimation is on the right.

From the above description, it can be seen that the realization of interpolation and decimation depends on the filter design. The filter is designed to meet the input and output amplitude stability and anti-spectral aliasing; what is more, filter efficiency is also an important factor needed to be considered, because it affects real-time signal processing [4, 5]. Two different digital filter designs will be discussed in the following part, the ordinary digital filter using a Hamming window FIR for design will be described first, and then the more efficient digital filter, including the CIC, half-band, and CIC compensation filter will be discussed after.

### 3.1 Hamming window FIR filter for decimation design

*f*

_{k}, which can be calculated by Eq. (3):

*f*

_{p}is set to 2.1 MHz in the system simulation, and in order to prevent the spectral aliasing caused by the spectrum extension after decimation, the passband and transition zone of the last stage are designed as follows:

Respectively, *f*_{p} and *f*_{stop} are the passband and stopband cutoff frequency for each stage. Therefore, calculating the order required for each stage of the filter, there will be more efficient digital filter design for decimation.

It can be seen that the third stage of the Hamming window digital filter whose order is up to 261, results in heavy calculations and poor real time. Therefore, a more efficient digital filter is taken into consideration. The CIC and half-band filter as more efficient filters are more common in multi-rate processing, of which the characteristics will be introduced in the following parts.

### 3.2 The more efficient digital filters

#### 3.2.1 CIC filter

CIC known as cascaded integrate comb is one kind of commonly used high efficiency filters, mainly applied when the decimation factor is not the power of 2. The reason for its high efficiency is that its coefficients are 1, so it requires no multiplier. Because of this, it is often used in multi-rate transformations of high-speed signal processing.

*D*is the decimation factor, and also representing the order of CIC, the transfer function on the Z-plane is:

*z*=

*e*

^{jω}into Eq. (9), we get the final amplitude frequency response:

*D*> > 1, the first side lobe amplitude is:

From Eq. (11), we can know the ratio of the main and side lobe amplitude is 3*π*/2; that is, the side lobe is only less than the main lobe with 13.46 dB. Therefore, the single CIC filter has a large side lobe amplitude, which generally cannot meet the system requirements. In order to reduce side lobe attenuation, a multi-stage CIC filter cascade is used to aid the design; for each additional stage of the CIC filter, side lobe attenuation will be reduced by 13.46 dB. In this design, five CIC filter cascades make the first side lobe attenuation up to 67 dB, which can basically meet the system requirements [6, 7].

#### 3.2.2 Half-band filter

*δ*

_{p}and

*δ*

_{s}are passband ripple and stopband ripple, respectively, and

*ω*

_{p}and

*ω*

_{A}are passband cutoff frequency and stopband cutoff frequency. The half-band filter has the following properties:

In conjunction with the spectral characteristics of the half-band filter, it can be seen that when *δ*_{p} = *δ*_{s} is small, as for a twofold decimation, the spectrum is twice stretched and then the 2*π* phase is shifted. Although the spectrum ranging from*π*/2 to *ω*_{A} is aliased to the signal in [*ω*_{p}, *π*/2], the signal located in passband [0, *ω*_{p}] can be recovered, so that the half-band filter can be used for twofold decimation. When the decimation factor is large and exactly the same as 2^{M}, an M-stage half-band filter cascade can be implemented [8].

The half-band filter ensures phase linearity and the coefficients of the filter are in even symmetry, which makes it possible to prove that all even coefficients except the center point coefficients are zero, which greatly reduces the amount of filter calculation and increases the real-time filter processing.

#### 3.2.3 CIC compensation filter

The received signal can be recovered after being processed by the digital frequency converter, which needs an appropriate design of filter parameters so that the signal waveform shape does not change significantly, but also needs to keep the amplitude of the signal within the fault tolerance range; therefore, the input and output gain remains at 0 dB.

*M*is set to 1 as default):

*f*represents the sampling rate before decimation,

*R*is the sampling rate transform factor, and

*N*is donated as the series of the CIC filter. The larger the parameter

*N*, the more uneven the passband is, so an inverse frequency response in the passband is needed to correct this unevenness [9, 10, 11]. Thus, the response function of the CIC compensation filter can be deduced according to Eq. (14).

From Eq. (15), when *R* → ∞, the compensation filter can be approximated as an inverse Singer function.

#### 3.2.4 Design scheme

Similarly, the coefficient of the half-band filter is generated using Matlab function “firhalfband” and also represented by an 18-bit fixed point.

## 4 Implementation of two multi-rate digital filter designs

### 4.1 Implementation of the Hamming window digital filter on FPGA

Parameters for each stage of the filter before the decimation

Filter parameters | First stage | Second stage | Third stage |
---|---|---|---|

Passband cutoff frequency (MHz) | 2.1 | 2.1 | 2.1 |

Stopband cutoff frequency(MHz) | 17.5 | 7.5 | 2.5 |

Filter order | 42 | 40 | 261 |

According to the above design of the Hamming window filter, in the hardware simulation, the input is written into the incentive test file by the way of the test input, and the output results are simulated by ModelSim. There are 240 two’s complement data values representing the two-tone signal as the test input; the output is also the two’s complement signal after filtering. The waveform of input and output is basically the same by the simulation tool, and the peak-to-peak amplitude is also close.

### 4.2 Implementation of the more efficient filter on FPGA

CIC filter parameters

Parameter name | Value |
---|---|

Conversion factor (R) | 3 |

Filter order (N) | 5 |

Differential delay (M) | 1 |

Input bit width (bit) | 16 |

Output bit width (bit) | 16 |

Output rounding option | Truncation |

*R*= 3, cascade stage

*N*= 5, and differential delay

*M*= 1. The bit width of the CIC filter output is related to the filter gain; for the decimation filter, the output gain is as follows.

By the calculation, a CIC decimation filter gain in this design of 243 can be obtained, that is 23.85 dB. The full-resolution output bit width is 24 bits; in order to get the result with the bit width of 16 bits, the least 8 bits should be truncated. Although some error exists in this processing, fortunately, the error can be calculated by analysis [12, 13].

^{17}; one bit represents the sign, and the upper 16 bits of the MSBs are intercepted and the low 19 bits of data is discarded (the maximum coefficient of the compensation filter is greater than 1, so 19 bits are used to store in the hardware actually).

The waveform characteristics of the signal after filtering can be preserved, but the amplitude of the signal will change. Fortunately, the amplitude error of each filter can be roughly estimated, so adding a simple multiplier at the last stage can compensate for the whole filter output. Using the same simulation method to test the Hamming window digital filter, compared to the more efficient digital filter in the calculation of time, has been greatly improved. The output delay of the Hamming window filter is 17.547 μs, while the more efficient filter is 4.550 μs, simulated on the same computer, with the processor Intel i3 Core, clock 2.4 GHz.

*η*, which can be calculated as follows.

where *v*_{in} and *v*_{out} are the difference of the maximum and minimum of the signal amplitude. From the simulation results of the design methods of two different digital filters, the amplitude range of the input signal is [− 6553, 6553] and the output range after decimation by the Hamming window filter is [− 4931, 5404], while the more efficient filter output range is [− 5463, 5923], so the amplitude errors are calculated, *η*_{1} = 0.211 and *η*_{2} = 0.131, respectively.

Performance comparison of two digital filtering methods in multi-rate design

Hamming window FIR | More efficient filter | ||
---|---|---|---|

Delay of input and output (μs) | 17.547 | 4.550 | |

Hardware resource occupancy | Total logic elements | 30,136 | 12,021 |

Total registers | 29,498 | 10,816 | |

Total memory bits | 1918 | 894 | |

Amplitude error | 0.211 | 0.131 |

## 5 Results and discussion

In this experiment, the digital filter is designed in multi-rate signal processing in digital down-conversion process and verified its performance on FPGA. Compared with conventional digital filter, the more efficient filter has a great advantage on the real time and the use of hardware resources, which can improve the real-time performance of the signal processing and greatly reduce the rate of the back-end digital signal processing. It is convenient and requires relatively small resources to implementation, which has great application prospect.

## Notes

### Funding

This research was supported by “Fundation of Graduate Innovation Center in Nanjing University of Aeronautics and Astronautics (KFJJ20181502)”.

### Availability of data and materials

Data sharing not applicable to this article as no datasets were generated or analyzed during the current study.

### Authors’ contributions

YL carried out the simulation and JT carried out the calculation study. QJ participated in the design of the whole experiments. All authors read and approved the final manuscript.

### Competing interests

The authors declare that they have no competing interests.

### Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

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