Design, Modeling, and Fabrication of High-Speed VCSEL with Data Rate up to 50 Gb/s
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We have studied the characteristics of frequency response at 850-nm GaAs high-speed vertical-cavity surface-emitting lasers (VCSELs) with different kinds of oxide aperture sizes and cavity length using the PICS3D simulation program. Using 5-μm oxide aperture sizes, the frequency response behavior can be improved from 18.4 GHz and 15.5 GHz to 21.2 GHz and 19 GHz in a maximum of 3 dB at 25 °C and 85 °C, respectively. Numerical simulation results also suggest that the frequency response performances improved from 21.2 GHz and 19 GHz to 30.5 GHz and 24.5 GHz in a maximum of 3 dB at 25 °C and 85 °C due to the reduction of cavity length from 3λ/2 to λ/2. Consequently, the high-speed VCSEL devices were fabricated on a modified structure and exhibited 50-Gb/s data rate at 85 °C.
KeywordsHigh-speed VCSEL PICS3D 50 Gb/s Oxide aperture Cavity length
Effective index method
Multiple quantum well
Photonic Integrated Circuit Simulator in 3D
Distributed Bragg reflector
Vertical-cavity surface-emitting lasers
In a few years, the vertical-cavity surface-emitting laser diodes (VCSELs) have become favorite transmitters for optical data links [1, 2]. Meanwhile, GaAs VCSEL devices have some advantages like low threshold current, power consumption, and small divergence angle, as well as top side illumination easily to make an array. Its demand has grown rapidly along with huge requirements for 5G Internet, 3D sensing, LiDAR, high-speed photodetectors, etc. [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14].
PICS3D (Photonic Integrated Circuit Simulator in 3D) is a state-of-the-art 3D simulator for laser diodes and related active photonic devices. PISC3D is a 3D comprehensive numerical solver offering rigorous and self-consistent treatment on thermal, electrical, and optical properties by solving the related equations based on the nonlinear Newton-Raphson method. Its primary goal is to provide a 3D simulator for edge- and surface-emitting laser diodes. It has also been expanded to include models for other components integrated with or related to the laser emitter. In this study, we simulated GaAs VCSEL; of course, it also expanded easily to GaN VCSEL, LED, etc. [15, 16].
The first oxidation process in III–V compound material was discovered at the University of Illinois at Urbana-Champaign by Dallesasse and Holonyak in 1989 . Through an oxidation process, the VCSEL devices can narrow down the size of oxide aperture diameter. Thus, it can not only promote a single transverse mode operation but also high-speed operation and single-mode performance.
To achieve a high modulation bandwidth, most designers would seek a large D-factor and reasonable low K-factor, typically a high differential gain by using strain QWs. A low photon lifetime by tuning the phase of the top distributed Bragg reflector (DBR) , a high confinement factor by employing a short cavity, and a small cavity oxide are necessary. On the other hand, reducing electrical parasitics can also improve modulation speed. These include parasitic capacitance from bond pads, intrinsic diode junction, and the area of out of aperture below metal contact pads which connects DBRs, oxidation layers, etc., and also include parasitic resistance from DBRs, junction resistance. However, parasitic resistance is not better as low as possible; it needs to match 50 Ohm impedance. Regarding the high-speed VCSEL device development for data communication, there are several papers that record the progress [19, 20]. Today, the state-of-the-art 50-Gb/s 850-nm VCSEL devices have been demonstrated successfully at Chalmers University of Technology (CUT) by Westbergh et al. and University of Illinois Urbana-Champaign (UIUC) by Feng et al. [21, 22, 23]. We compared our experiments’ result in this study with other labs, and our data is much close to their results.
However, the most effective way to increase the differential gain is the use of strain multiple quantum well (MQW), such as replacing the GaAs/AlGaAs MQW by the InGaAs/AlGaAs MQW [24, 25]. In the GaAs-based material, the hole effective mass is much larger than the electron effective mass, which causes the quasi-Fermi level to separate toward the valance band . Hence, if we implement the strain on an active layer, the effective hole mass can be reduced significantly because the separation of the quasi-Fermi level is more balanced between the conduction and valance band. The differential gain can be considered as the growth of gain with carrier density once the quasi-Fermi level separation becomes more symmetric, and in the meanwhile, the differential gain will become more compressive in the strained MQW. Furthermore, the strain will also release the valance band mixing effect by increasing the energy difference between the heavy hole and light hole band. In this study, the numerical simulation was optimized to the VCSEL device structure through Crosslight PICS3D software .
Results and Discussion
The D-factor is an important parameter which related to internal quantum efficiency and the differential gain of the quantum wells for VCSEL operating at high speed . Thus, the D-factor was 6.9, 7.3, and 11 GHz/mA1/2 at 25 °C for VCSEL A, B, and C devices, respectively. On the other hand, the D-factor was 6.0, 6.7, and 9.4 GHz/mA1/2 at 85 °C for VCSEL A, B, and C devices, respectively. From our results, the D-factor is inversely proportional to the oxide aperture diameter and cavity length. And the larger D-factor will be along with smaller threshold current. Furthermore, the VCSELs with smaller oxide aperture diameters (5 μm) and shorter cavity length (λ/2) are especially well-suited for data transmission at low energy per bit [30, 31, 32]. We expect the VCSEL can achieve error-free operation rate up to 50 Gb/s.
In conclusion, we optimized the oxide aperture and cavity length of the VCSEL structure by the PICS3D simulation program. Referring to these results, we fabricated 50-Gb/s VCSEL devices. The results showed a decrease in threshold current and improvement of 3-dB bandwidth in VCSEL devices. Finally, the high-speed VCSEL devices (up to 50-Gb/s data rate at 85 °C) had been demonstrated and successfully to create PICS3D model for 50-Gb/s VCSEL device design.
We would like to thank Prof. Kenichi Iga and Prof. Fumio Koyama of Tokyo Institute of Technology, Prof. N. Holonyak Jr. and Prof. M. Feng of UIUC for giving us recommendations of high-speed VCSEL device physical models, Prof. C. Chang-Hasnain of UC Berkeley, and Prof. S. C. Wang and Prof. T. C. Lu of National Chiao Tung University to discuss the devices’ structures, etc. Finally, we appreciate Crosslight for providing support of the simulation modeling tool.
CCS, TCH, YWY, CYK, YTL, HWL, HYT, YTC, CHW, PTL, CCL, CHC, and HCK discussed the topic and experiments. YWY and YTL did the PICS3D simulations and consulted YS for the PICS3D tool. CHW manufactured and measured the devices. All authors discussed the data analysis and interpretation and contributed equally to the writing of the manuscript. All authors approved the final version of the manuscript.
The funding was supported by the Ministry of Science and Technology of Taiwan. The grant number is MOST 106-2218-E-005-001-.
The authors declare that they have no competing interests.
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